ADVANCED AND EVER ADVANCING
MITSUBISHI ELECTRIC
MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES
38B5
Group
User's Manual
MITSUBISHI ELECTRIC
keep safety first in your circuit designs ! q Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials q These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. q Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. q All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. q Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. q The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. q If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of JAPAN and/or the country of destination is prohibited. q Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
Preface
This user's manual describes Mitsubishi's CMOS 8bit microcomputers 38B5 Group. After reading this manual, the user should have a through knowledge of the functions and features of the 38B5 Group, and should be able to fully utilize the product. The manual starts with specifications and ends with application examples. For details of software, refer to the "740 Family Software Manual." For details of development support tools, refer to the "DEVELOPMENT SUPPORT TOOLS FOR MICROCOMPUTERS" data book.
BEFORE USING THIS USER'S MANUAL
This user's manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development.
1. Organization
q CHAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function. q CHAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions, based mainly on setting examples of relevant registers. q CHAPTER 3 APPENDIX This chapter includes a list of registers, and necessary information for systems development using the microcomputer, the mask ROM confirmation (for mask ROM version), ROM programming confirmation, and the mark specifications which are to be submitted when ordering.
2. Structure of Register
The figure of each register structure describes its functions, contents at reset, and attributes as follows:
(Note 2)
Bits
b7 b6 b5 b4 b3 b2 b1 b0 0
Bit attributes
(Note 1)
Contents immediately after reset release
CPU mode register (CPUM) [Address : 3B 16] b 0 1 2 3 4 5 6 7 Stack page selection bit Name Processor mode bits
b1 b0
Functions
0 0 : Single-chip mode 01: Not available 10: 11: 0 : 0 page 1 : 1 page
At reset
RW
0 0 0 0 0 0
! !
Nothing arranged for these bits. These are write disabled bits. When these bits are read out, the contents are "0." Fix this bit to "0." Main clock division ratio selection bits
0 0 : = XIN/2 (High-speed mode) 0 1 : = XIN/8 (Middle-speed mode) 1 0 : = XIN/8 (Middle-speed mode) 1 1 : = XIN (Double-speed mode)
b7 b6
1 0
: Bit in which nothing is arranged
: Bit that is not used for control of the corresponding function
Notes 1: Contents immediately after reset release 0******"0" at reset release 1******"1" at reset release Undefined******Undefined or reset release T ******Contents determined by option at reset release 2: Bit attributes******The attributes of control register bits are classified into 3 bytes : read-only, write-only and read and write. In the figure, these attributes are represented as follows : R******Read ******Read enabled !******Read disabled W******Write ******Write enabled ! ******Write disabled
Table of contents
Table of contents
CHAPTER 1 HARDWARE
DESCRIPTION ................................................................................................................................ 1-2 FEATURES .................................................................................................................................... 1-2 APPLICATION ................................................................................................................................ 1-2 PIN CONFIGURATION .................................................................................................................. 1-2 FUNCTIONAL BLOCK .................................................................................................................. 1-3 PIN DESCRIPTION ........................................................................................................................ 1-4 PART NUMBERING ....................................................................................................................... 1-6 GROUP EXPANSION .................................................................................................................... 1-7 Memory Type ............................................................................................................................ 1-7 Memory Size ............................................................................................................................. 1-7 Package ..................................................................................................................................... 1-7 FUNCTIONAL DESCRIPTION ...................................................................................................... 1-8 Central Processing Unit (CPU) .............................................................................................. 1-8 Memory .................................................................................................................................... 1-12 I/O Ports .................................................................................................................................. 1-14 Interrupts ................................................................................................................................. 1-20 Timers ...................................................................................................................................... 1-23 Serial I/O ................................................................................................................................. 1-28 FLD Controller ........................................................................................................................ 1-40 A-D Converter ......................................................................................................................... 1-52 Pulse Width Modulation (PWM) ........................................................................................... 1-53 Interrupt Interval Determination Function ............................................................................ 1-56 Watchdog Timer ..................................................................................................................... 1-58 Buzzer Output Circucit .......................................................................................................... 1-59 Reset Circuit ........................................................................................................................... 1-60 Clock Generating Circuit ....................................................................................................... 1-62 NOTES ON PROGRAMMING ..................................................................................................... 1-65 NOTES ON USE .......................................................................................................................... 1-65 DATA REQUIRED FOR MASK ORDERS ................................................................................ 1-66 DATA REQUIRED FOR ROM WRITING ORDERS ................................................................. 1-66 ROM PROGRAMMING METHOD .............................................................................................. 1-66 MASK OPTION OF PULL-DOWN RESISTOR ......................................................................... 1-67 FUNCTIONAL DESCRIPTION SUPPLEMENT ......................................................................... 1-69
CHAPTER 2 APPLICATION
2.1 I/O port ..................................................................................................................................... 2-2 2.1.1 Memory assignment ....................................................................................................... 2-2 2.1.2 Relevant registers .......................................................................................................... 2-3 2.1.3 Terminate unused pins .................................................................................................. 2-6 2.1.4 Notes on use .................................................................................................................. 2-7 2.1.5 Termination of unused pins .......................................................................................... 2-8 2.2 Timer....................................................................................................................................... 2-10 2.2.1 Memory map ................................................................................................................. 2-10 2.2.2 Relevant registers ........................................................................................................ 2-11
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2.2.3 Timer application examples ........................................................................................ 2-19 2.3 Serial I/O ................................................................................................................................ 2-35 2.3.1 Memory map ................................................................................................................. 2-35 2.3.2 Relevant registers ........................................................................................................ 2-36 2.3.3 Serial I/O1 connection examples ............................................................................... 2-47 2.3.4 Serial I/O1's modes ..................................................................................................... 2-49 2.3.5 Serial I/O1 application examples ............................................................................... 2-50 2.3.6 Serial I/O2 connection examples ............................................................................... 2-56 2.3.7 Serial I/O2's modes ..................................................................................................... 2-58 2.3.8 Serial I/O2 application examples ............................................................................... 2-59 2.3.9 Notes on serial I/O1 .................................................................................................... 2-78 2.3.10 Notes on serial I/O2 .................................................................................................. 2-80 2.4 FLD controller ...................................................................................................................... 2-83 2.4.1 Memory assignment ..................................................................................................... 2-83 2.4.2 Relevant registers ........................................................................................................ 2-84 2.4.3 FLD controller application examples ......................................................................... 2-93 2.4.4 Notes on use .............................................................................................................. 2-124 2.5 A-D converter ..................................................................................................................... 2-125 2.5.1 Memory assignment ................................................................................................... 2-125 2.5.2 Relevant registers ...................................................................................................... 2-125 2.5.3 A-D converter application examples ........................................................................ 2-129 2.5.4 Notes on use .............................................................................................................. 2-131 2.6 PWM ...................................................................................................................................... 2-132 2.6.1 Memory assignment ................................................................................................... 2-132 2.6.2 Relevant registers ...................................................................................................... 2-132 2.6.3 PWM application example ......................................................................................... 2-134 2.6.4 Notes on use .............................................................................................................. 2-135 2.7 Interrupt interval determination function ..................................................................... 2-136 2.7.1 Memory assignment ................................................................................................... 2-136 2.7.2 Relevant registers ...................................................................................................... 2-136 2.7.3 Interrupt interval determination function application examples ............................ 2-140 2.8 Watchdog timer .................................................................................................................. 2-144 2.8.1 Memory assignment ................................................................................................... 2-144 2.8.2 Relevant register ........................................................................................................ 2-144 2.8.3 Watchdog timer application examples ..................................................................... 2-145 2.8.4 Notes on use .............................................................................................................. 2-146 2.9 Buzzer output circuit ........................................................................................................ 2-147 2.9.1 Memory assignment ................................................................................................... 2-147 2.9.2 Relevant register ........................................................................................................ 2-147 2.9.3 Buzzer output circuit application examples ............................................................ 2-148 2.10 Reset circuit ..................................................................................................................... 2-149 2.10.1 Connection example of reset IC ............................................................................ 2-149 2.10.2 Notes on use ............................................................................................................ 2-150 2.11 Clock generating circuit ................................................................................................ 2-151 2.11.1 Relevant register ...................................................................................................... 2-151 2.11.2 Clock generating circuit application examples ..................................................... 2-152
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Table of contents CHAPTER 3 APPENDIX
3.1 Electrical characteristics ..................................................................................................... 3-2 3.1.1 Absolute maximum ratings ............................................................................................ 3-2 3.1.2 Recommended operating conditions ............................................................................ 3-3 3.1.3 Electrical characteristics ................................................................................................ 3-4 3.1.4 A-D converter characteristics ....................................................................................... 3-5 3.1.5 Timing requirements and switching characteristics ................................................... 3-6 3.2 Standard characteristics ...................................................................................................... 3-8 3.2.1 Power source current standard characteristics .......................................................... 3-8 3.2.2 Port standard characteristics ........................................................................................ 3-9 3.2.3 A-D conversion standard characteristics ................................................................... 3-13 3.3 Notes on use ........................................................................................................................ 3-14 3.3.1 Notes on interrupts ...................................................................................................... 3-14 3.3.2 Notes on serial I/O1 .................................................................................................... 3-15 3.3.3 Notes on serial I/O2 .................................................................................................... 3-16 3.3.4 Notes on FLD controller .............................................................................................. 3-19 3.3.5 Notes on A-D converter .............................................................................................. 3-19 3.3.6 Notes on PWM ............................................................................................................. 3-19 3.3.7 Notes on watchdog timer ............................................................................................ 3-20 3.3.8 Notes on reset circuit .................................................................................................. 3-20 3.3.9 Notes on input and output pins ................................................................................. 3-20 3.3.10 Notes on programming .............................................................................................. 3-22 3.3.11 Programming and test of built-in PROM version................................................... 3-23 3.3.12 Notes on built-in PROM version .............................................................................. 3-24 3.3.13 Termination of unused pins ...................................................................................... 3-25 3.4 Countermeasures against noise ...................................................................................... 3-26 3.4.1 Shortest wiring length .................................................................................................. 3-26 3.4.2 Connection of bypass capacitor across VSS line and VCC line ............................... 3-28 3.4.3 Wiring to analog input pins ........................................................................................ 3-29 3.4.4 Oscillator concerns....................................................................................................... 3-29 3.4.5 Setup for I/O ports ....................................................................................................... 3-31 3.4.6 Providing of watchdog timer function by software .................................................. 3-32 3.5 Control registers .................................................................................................................. 3-33 3.6 Mask ROM confirmation form........................................................................................... 3-67 3.7 ROM programming confirmation form ............................................................................ 3-75 3.8 Mark specification form ..................................................................................................... 3-77 3.9 Package outline ................................................................................................................... 3-78 3.10 List of instruction code ................................................................................................... 3-79 3.11 Machine instructions ........................................................................................................ 3-80 3.12 M35501FP ............................................................................................................................ 3-91 3.13 SFR memory map ............................................................................................................ 3-103 3.14 Pin configuration ............................................................................................................. 3-104
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List of figures
List of figures
CHAPTER 1 HARDWARE
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 1 Pin configuration of M38B5xMxH-XXXXFP ..................................................................... 1-2 2 Functional block diagram ................................................................................................... 1-3 3 Part numbering .................................................................................................................... 1-6 4 Memory expansion plan ..................................................................................................... 1-7 5 740 Family CPU register structure ................................................................................... 1-8 6 Register push and pop at interrupt generation and subroutine call ........................... 1-9 7 Structure of CPU mode register ..................................................................................... 1-11 8 Memory map diagram ...................................................................................................... 1-12 9 Memory map of special function register (SFR) .......................................................... 1-13 10 Structure of pull-up control registers (PULL1 and PULL2) ...................................... 1-14 11 Port block diagram (1) ................................................................................................... 1-17 12 Port block diagram (2) ................................................................................................... 1-18 13 Port block diagram (3) ................................................................................................... 1-19 14 Interrupt control ............................................................................................................... 1-22 15 Structure of interrupt related registers ........................................................................ 1-22 16 Structure of timer related register ................................................................................ 1-23 17 Block diagram of timer .................................................................................................. 1-24 18 Timing chart of timer 6 PWM1 mode ........................................................................... 1-25 19 Block diagram of timer X .............................................................................................. 1-27 20 Structure of timer X related registers .......................................................................... 1-27 21 Block diagram of serial I/O1 ......................................................................................... 1-28 22 Structure of serail I/O1 control registers 1, 2 ............................................................ 1-29 23 Structure of serial I/O1 control register 3 ................................................................... 1-30 24 Structure of serial I/O1 automatic transfer data pointer ........................................... 1-31 25 Automatic transfer serial I/O operation ....................................................................... 1-32 26 SSTB1 output operation .................................................................................................... 1-33 27 SBUSY1 input operation (internal synchronous clock) ................................................... 1-33 28 SBUSY1 input operation (external synchronous clock) .................................................. 1-33 29 SBUSY1 output operation (internal synchronous clock, 8-bits serial I/O) ................... 1-34 30 SBUSY1 output operation (external synchronous clock, 8-bits serial I/O) .................. 1-34 31 SBUSY1 output operation in automatic transfer serial I/O mode (internal synchronous clock, SBUSY1 output function outputs each 1-byte) ................................................... 1-34 32 SRDY1 output operation .................................................................................................... 1-35 33 SRDY1 input operation (internal synchronous clock) .................................................... 1-35 34 Handshake operation at serial I/O1 mutual connecting (1) ...................................... 1-36 35 Handshake operation at serial I/O1 mutual connecting (2) ...................................... 1-36 36 Block diagram of clock snchronous serial I/O2 ......................................................... 1-37 37 Operation of clock synchronous serial I/O2 function ................................................ 1-37 38 Block diagram of UART serial I/O2 ............................................................................. 1-38 39 Operation of UART serial I/O2 function ...................................................................... 1-38 40 Structure of serial I/O2 related register ...................................................................... 1-39 41 Block diagram for FLD control circuit .......................................................................... 1-40 42 Structure of FLDC mode register ................................................................................. 1-41 43 Segment/Digit setting example ..................................................................................... 1-42 44 FLD automatic display RAM assignment .................................................................... 1-43 45 Example of using FLD automatic display RAM in 16-timing*ordinary mode ......... 1-44
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List of figures
Fig. 46 Example of using FLD automatic display RAM in 16-timing*gradation display mode ........................................................................................................................................................ 1-45 Fig. 47 Example of using FLD automatic display RAM in 32-timing mode ......................... 1-46 Fig. 48 Structure of FLDRAM write disable register ............................................................... 1-47 Fig. 49 Example of digit timing using grid scan type ............................................................. 1-48 Fig. 50 Example of using FLD automatic display RAM using grid scan type .................... 1-48 Fig. 51 FLDC timing .................................................................................................................... 1-50 Fig. 52 P84 to P87 FLD output waveform ................................................................................. 1-51 Fig. 53 Structure of port P8 FLD output control register ....................................................... 1-51 Fig. 54 Structure of A-D control register .................................................................................. 1-52 Fig. 55 Black diagram of A-D converter ................................................................................... 1-52 Fig. 56 PWM block diagram ....................................................................................................... 1-53 Fig. 57 PWM timing ..................................................................................................................... 1-54 Fig. 58 Structure of PWM control register ............................................................................... 1-55 Fig. 59 14-bit PWM timing .......................................................................................................... 1-55 Fig. 60 Interrupt interval determination circuit block diagram ............................................... 1-56 Fig. 61 Structure of itnerrupt interval determination control register .................................... 1-57 Fig. 62 Interrupt inteval determination operation example (at rising edge active) ............. 1-57 Fig. 63 Interrupt interval determination operation example (at both-sided edge active) ... 1-57 Fig. 64 Block diagram of watchdog timer ................................................................................. 1-58 Fig. 65 Structure of watchdog timer control register .............................................................. 1-58 Fig. 66 Block diagram of buzzer output circuit ........................................................................ 1-59 Fig. 67 Structure of buzzer output control register ................................................................ 1-59 Fig. 68 Reset circuit example .................................................................................................... 1-60 Fig. 69 Reset sequence .............................................................................................................. 1-60 Fig. 70 Internal status at reset .................................................................................................. 1-61 Fig. 71 Ceramic resonator circuit .............................................................................................. 1-62 Fig. 72 External clock input circuit ............................................................................................ 1-62 Fig. 73 Clock generating circuit block diagram ....................................................................... 1-63 Fig. 74 State transitions of system clock ................................................................................. 1-64 Fig. 75 Programming and testing of One Time PROM version ............................................ 1-66 Fig. 76 Digit timing waveform (1) .............................................................................................. 1-67 Fig. 77 Digit timing waveform (2) .............................................................................................. 1-68 Fig. 78 Timing chart after interrupt occurs ............................................................................... 1-70 Fig. 79 TIme up to execution of interrupt processing routine ............................................... 1-70 Fig. 80 A-D conversion equivalent circuit ................................................................................. 1-72 Fig. 81 A-D conversion timing chart.......................................................................................... 1-72
CHAPTER 2 APPLICATION
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.1.7 2.1.8 2.1.9 2.2.1 Memory assignment of I/O port relevant registers .................................................. 2-2 Structure of port Pi (i = 0, 1, 2, 3, 4, 5, 7, 8) ........................................................ 2-3 Structure of port P6 ..................................................................................................... 2-3 Structure of port P9 ..................................................................................................... 2-3 Structure of port Pi (i = 0, 2, 4, 5, 7, 8) direction register ................................... 2-4 Structure of port P6 direction register ...................................................................... 2-4 Structure of port P9 direction register ...................................................................... 2-5 Structure of pull-up control register 1 ....................................................................... 2-5 Structure of pull-up control register 2 ....................................................................... 2-6 Memory map of registers relevant to timers .......................................................... 2-10
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List of figures
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.2.2 Structure of Timer i (i=1, 3, 4, 5, 6) ....................................................................... 2-11 2.2.3 Structure of Timer 2 .................................................................................................. 2-11 2.2.4 Structure of Timer 6 PWM register ......................................................................... 2-11 2.2.5 Structure of Timer 12 mode register ....................................................................... 2-12 2.2.6 Structure of Timer 34 mode register ....................................................................... 2-12 2.2.7 Structure of Timer 56 mode register ....................................................................... 2-13 2.2.8 Structure of Timer X (low-order, high-order) .......................................................... 2-13 2.2.9 Structure of Timer X mode register 1 ..................................................................... 2-14 2.2.10 Structure of Timer X mode register 2 ................................................................... 2-15 2.2.11 Structure of Interrupt request register 1 ............................................................... 2-16 2.2.12 Structure of Interrupt request register 2 ............................................................... 2-17 2.2.13 Structure of Interrupt control register 1 ................................................................ 2-18 2.2.14 Structure of Interrupt control register 2 ................................................................ 2-18 2.2.15 Timers connection and setting of division ratios ................................................. 2-20 2.2.16 Relevant registers setting ....................................................................................... 2-21 2.2.17 Control procedure..................................................................................................... 2-22 2.2.18 Peripheral circuit example ....................................................................................... 2-23 2.2.19 Timers connection and setting of division ratios ................................................. 2-23 2.2.20 Relevant registers setting ....................................................................................... 2-24 2.2.21 Control procedure..................................................................................................... 2-24 2.2.22 Judgment method of valid/invalid of input pulses ............................................... 2-25 2.2.23 Relevant registers setting ....................................................................................... 2-26 2.2.24 Control procedure..................................................................................................... 2-27 2.2.25 Timers connection and setting of division ratios ................................................. 2-28 2.2.26 Relevant registers setting ....................................................................................... 2-29 2.2.27 Control procedure..................................................................................................... 2-30 2.2.28 Timers connection and table example of timer X/RTP setting values ............. 2-32 2.2.29 RTP output example ................................................................................................ 2-32 2.2.30 Relevant registers setting ....................................................................................... 2-33 2.2.31 Control procedure..................................................................................................... 2-34 2.3.1 Memory map of registers relevant to Serial I/O .................................................... 2-35 2.3.2 Structure of Serial I/O1 automatic transfer data pointer ...................................... 2-36 2.3.3 Structure of Serial I/O1 control register 1 .............................................................. 2-37 2.3.4 Structure of Serial I/O1 control register 2 .............................................................. 2-38 2.3.5 Structure of Serial I/O1 register/Transfer counter ................................................. 2-39 2.3.6 Structure of Serial I/O1 control register 3 .............................................................. 2-40 2.3.7 Structure of Baud rate generator ............................................................................. 2-41 2.3.8 Structure of UART control register .......................................................................... 2-41 2.3.9 Structure of Serial I/O2 control register.................................................................. 2-42 2.3.10 Structure of Serial I/O2 status register ................................................................. 2-43 2.3.11 Structure of Serial I/O2 transmit/receive buffer register ..................................... 2-43 2.3.12 Structure of Interrupt source switch register ........................................................ 2-44 2.3.13 Structure of Interrupt request register 1 ............................................................... 2-44 2.3.14 Structure of Interrupt request register 2 ............................................................... 2-45 2.3.15 Structure of Interrupt control register 1 ................................................................ 2-46 2.3.16 Structure of Interrupt control register 2 ................................................................ 2-46 2.3.17 Serial I/O1 connection examples (1) ..................................................................... 2-47 2.3.18 Serial I/O1 connection examples (2) ..................................................................... 2-48 2.3.19 Serial I/O1's modes ................................................................................................. 2-49 2.3.20 Connection diagram ................................................................................................. 2-50 2.3.21 Timing chart .............................................................................................................. 2-50
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List of figures
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.3.22 Registers setting relevant to transmission side ................................................... 2-51 2.3.23 Setting of transmission data ................................................................................... 2-51 2.3.24 Control procedure..................................................................................................... 2-52 2.3.25 Connection diagram ................................................................................................. 2-53 2.3.26 Timing chart of serial data transmission/reception .............................................. 2-53 2.3.27 Relevant registers setting ....................................................................................... 2-54 2.3.28 Control procedure ..................................................................................................... 2-55 2.3.29 Serial I/O2 connection examples (1) ..................................................................... 2-56 2.3.30 Serial I/O2 connection examples (2) ..................................................................... 2-57 2.3.31 Serial I/O2's modes ................................................................................................. 2-58 2.3.32 Serial I/O2 transfer data format ............................................................................. 2-58 2.3.33 Connection diagram ................................................................................................. 2-59 2.3.34 Timing chart .............................................................................................................. 2-59 2.3.35 Registers setting relevant to transmission side ................................................... 2-60 2.3.36 Registers setting relevant to reception side......................................................... 2-61 2.3.37 Control procedure of transmission side ................................................................ 2-62 2.3.38 Control procedure of reception side ...................................................................... 2-63 2.3.39 Connection diagram ................................................................................................. 2-64 2.3.40 Timing chart .............................................................................................................. 2-64 2.3.41 Relevant registers setting ....................................................................................... 2-65 2.3.42 Setting of transmission data ................................................................................... 2-65 2.3.43 Control procedure..................................................................................................... 2-66 2.3.44 Connection diagram ................................................................................................. 2-67 2.3.45 Timing chart .............................................................................................................. 2-68 2.3.46 Relevant registers setting in master unit .............................................................. 2-68 2.3.47 Relevant registers setting in slave unit ................................................................ 2-69 2.3.48 Control procedure of master unit ........................................................................... 2-70 2.3.49 Control procedure of slave unit ............................................................................. 2-71 2.3.50 Connection diagram ................................................................................................. 2-72 2.3.51 Timing chart .............................................................................................................. 2-72 2.3.52 Registers setting relevant to transmission side ................................................... 2-74 2.3.53 Registers setting relevant to reception side......................................................... 2-75 2.3.54 Control procedure of transmission side ................................................................ 2-76 2.3.55 Control procedure of reception side ...................................................................... 2-77 2.3.56 Sequence of setting serial I/O2 control register again ....................................... 2-81 2.4.1 Memory assignment of FLD controller relevant registers ..................................... 2-83 2.4.2 Structure of P1FLDRAM write disable register ...................................................... 2-84 2.4.3 Structure of P3FLDRAM write disable register ...................................................... 2-85 2.4.4 Structure of FLD mode register ............................................................................... 2-86 2.4.5 Structure of Tdisp time set register ......................................................................... 2-87 2.4.6 Structure of Toff1 time set register ......................................................................... 2-88 2.4.7 Structure of Toff2 time set register ......................................................................... 2-88 2.4.8 Structure of FLD data pointer/FLD data pointer reload register ......................... 2-89 2.4.9 Structure of port P0FLD/port switch register .......................................................... 2-89 2.4.10 Structure of port P2FLD/port switch register ....................................................... 2-90 2.4.11 Structure of port P8FLD/port switch register ....................................................... 2-90 2.4.12 Structure of port P8FLD output control register .................................................. 2-91 2.4.13 Structure of interrupt request register 2 ............................................................... 2-91 2.4.14 Structure of interrupt control register 2 ................................................................ 2-92 2.4.15 Connection diagram ................................................................................................. 2-93 2.4.16 Timing chart of key-scan using FLD automatic display mode and segments . 2-93
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List of figures
Fig. 2.4.17 Enlarged view of FLD0 (P20) to FLD7 (P27) Tscan .............................................. 2-93 Fig. 2.4.18 Setting of relevant registers ................................................................................... 2-94 Fig. 2.4.19 FLD digit allocation example .................................................................................. 2-97 Fig. 2.4.20 Control procedure..................................................................................................... 2-98 Fig. 2.4.21 Connection diagram ............................................................................................... 2-100 Fig. 2.4.22 Timing chart of key-scan using FLD automatic display mode and digits ...... 2-101 Fig. 2.4.23 Setting of relevant registers ................................................................................. 2-102 Fig. 2.4.24 FLD digit allocation example ................................................................................ 2-105 Fig. 2.4.25 Control procedure................................................................................................... 2-106 Fig. 2.4.26 Connection diagram ............................................................................................... 2-108 Fig. 2.4.27 Timing chart of FLD display by software ........................................................... 2-108 Fig. 2.4.28 Enlarged view of P20 to P27 key-scan ................................................................ 2-108 Fig. 2.4.29 Setting of relevant registers ................................................................................. 2-109 Fig. 2.4.30 FLD digit allocation example ................................................................................ 2-110 Fig. 2.4.31 Control procedure................................................................................................... 2-111 Fig. 2.4.32 Connection diagram ............................................................................................... 2-112 Fig. 2.4.33 Timing chart of 38B5 Group and M35501FP ..................................................... 2-113 Fig. 2.4.34 Timing chart (enlarged view) of digit and segment output .............................. 2-113 Fig. 2.4.35 Setting of relevant registers ................................................................................. 2-114 Fig. 2.4.36 FLD digit allocation example ................................................................................ 2-117 Fig. 2.4.37 Control procedure................................................................................................... 2-117 Fig. 2.4.38 Connection diagram ............................................................................................... 2-118 Fig. 2.4.39 Timing chart (at correct state) of 38B5 Group and M35501FP ...................... 2-119 Fig. 2.4.40 Timing chart (at incorrect state) of 38B5 Group and M35501FP ................... 2-119 Fig. 2.4.41 Setting of relevant registers ................................................................................. 2-120 Fig. 2.4.42 Control procedure................................................................................................... 2-122 Fig. 2.5.1 Memory assignment of A-D converter relevant registers ................................... 2-125 Fig. 2.5.2 Structure of A-D control register ............................................................................ 2-125 Fig. 2.5.3 Structure of A-D conversion register (low-order) ................................................. 2-126 Fig. 2.5.4 Structure of A-D conversion register (high-order) ............................................... 2-126 Fig. 2.5.5 Structure of interrupt request register 2 ............................................................... 2-127 Fig. 2.5.6 Structure of interrupt control register 2 ................................................................ 2-128 Fig. 2.5.7 Connection diagram ................................................................................................. 2-129 Fig. 2.5.8 Setting of relevant registers ................................................................................... 2-129 Fig. 2.5.9 Control procedure ..................................................................................................... 2-130 Fig. 2.6.1 Memory assignment of PWM relevant registers .................................................. 2-132 Fig. 2.6.2 Structure of PWM register (high-order) ................................................................. 2-132 Fig. 2.6.3 Structure of PWM register (low-order) .................................................................. 2-133 Fig. 2.6.4 Structure of PWM control register ......................................................................... 2-133 Fig. 2.6.5 Connection diagram ................................................................................................. 2-134 Fig. 2.6.6 Setting of relevant registers ................................................................................... 2-134 Fig. 2.6.7 Control procedure ..................................................................................................... 2-135 Fig. 2.6.8 PWM0 output ............................................................................................................. 2-135 Fig. 2.7.1 Memory assignment of interrupt interval determination function relevant registers ...................................................................................................................................................... 2-136 Fig. 2.7.2 Structure of interrupt interval determination register........................................... 2-136 Fig. 2.7.3 Structure of interrupt interval determination control register ............................. 2-137 Fig. 2.7.4 Structure of interrupt edge selection register....................................................... 2-137 Fig. 2.7.5 Structure of interrupt request register 1 ............................................................... 2-138 Fig. 2.7.6 Structure of interrupt control register 1 ................................................................ 2-139 Fig. 2.7.7 Connection diagram ................................................................................................. 2-140
38B5 Group User's Manual
v
List of figures
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.7.8 Function block diagram ........................................................................................... 2-140 2.7.9 Timing chart of data determination ........................................................................ 2-140 2.7.10 Setting of relevant registers ................................................................................. 2-141 2.7.11 Control procedure................................................................................................... 2-142 2.7.12 Reception of remote-control data (timer 2 interrupt) ........................................ 2-143 2.8.1 Memory assignment of watchdog timer relevant register ................................... 2-144 2.8.2 Structure of watchdog timer control register ........................................................ 2-144 2.8.3 Connection of watchdog timer and setting of division ratio ............................... 2-145 2.8.4 Setting of relevant registers ................................................................................... 2-145 2.8.5 Control procedure ..................................................................................................... 2-146 2.9.1 Memory assignment of buzzer output circuit relevant register .......................... 2-147 2.9.2 Structure of buzzer output control register ........................................................... 2-147 2.9.3 Connection of buzzer output circuit and setting of division ratio ...................... 2-148 2.9.4 Setting of relevant register ..................................................................................... 2-148 2.9.5 Control procedure ..................................................................................................... 2-148 2.10.1 Example of power-on reset circuit ....................................................................... 2-149 2.10.2 RAM backup system example .............................................................................. 2-149 2.11.1 Structure of CPU mode register .......................................................................... 2-151 2.11.2 Connection diagram ............................................................................................... 2-152 2.11.3 Status transition diagram during power failure .................................................. 2-152 2.11.4 Setting of relevant registers ................................................................................. 2-153 2.11.5 Control procedure................................................................................................... 2-154 2.11.6 Structure of clock counter ..................................................................................... 2-155 2.11.7 Initial setting of relevant registers ....................................................................... 2-156 2.11.8 Setting of relevant registers after detecting power failure ............................... 2-157 2.11.9 Control procedure................................................................................................... 2-158
CHAPTER 3 APPENDIX
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.1.1 Circuit for measuring output switching characteristics ............................................ 3-6 3.1.2 Timing diagram ............................................................................................................. 3-7 3.2.1 Power source current standard characteristics ........................................................ 3-8 3.2.2 Power source current standard characteristics (in wait mode) ............................. 3-8 3.2.3 High-breakdown P-channel open-drain output port characteristics (25 C) ......... 3-9 3.2.4 High-breakdown P-channel open-drain output port characteristics (90 C) ......... 3-9 3.2.5 CMOS output port P-channel side characteristics (25 C) .................................. 3-10 3.2.6 CMOS output port P-channel side characteristics (90 C) .................................. 3-10 3.2.7 CMOS output port N-channel side characteristics (25 C) .................................. 3-11 3.2.8 CMOS output port N-channel side characteristics (90 C) .................................. 3-11 3.2.9 N-channel open-drain output port characteristics (25 C) .................................... 3-12 3.2.10 N-channel open-drain output port characteristics (90 C).................................. 3-12 3.2.11 A-D conversion standard characteristics............................................................... 3-13 3.3.1 Sequence of switch detection edge ......................................................................... 3-14 3.3.2 Sequence of check of interrupt request bit ............................................................ 3-14 3.3.3 Structure of interrupt control register 2 .................................................................. 3-15 3.3.4 Sequence of setting serial I/O2 control register again ......................................... 3-18 3.3.5 PWM output ................................................................................................................ 3-19 3.3.6 Initialization of processor status register ................................................................ 3-22 3.3.7 Sequence of PLP instruction execution .................................................................. 3-22 3.3.8 Stack memory contents after PHP instruction execution ..................................... 3-22
vi
38B5 Group User's Manual
List of figures
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.3.9 Status flag at decimal calculations .......................................................................... 3-23 3.3.10 Programming and testing of One Time PROM version ...................................... 3-23 3.4.1 Selection of packages ............................................................................................... 3-26 3.4.2 Wiring for the RESET pin ......................................................................................... 3-26 3.4.3 Wiring for clock I/O pins ........................................................................................... 3-27 3.4.4 Wiring for the VPP pin of the One Time PROM and the EPROM version ......... 3-28 3.4.5 Bypass capacitor across the VSS line and the VCC line ........................................ 3-28 3.4.6 Analog signal line and a resistor and a capacitor ................................................ 3-29 3.4.7 Wiring for a large current signal line ...................................................................... 3-29 3.4.8 Wiring of signal lines where potential levels change frequently ......................... 3-30 3.4.9 VSS pattern on the underside of an oscillator ........................................................ 3-30 3.4.10 Setup for I/O ports ................................................................................................... 3-31 3.4.11 Watchdog timer by software ................................................................................... 3-32 3.5.1 Structure of port Pi .................................................................................................... 3-33 3.5.2 Structure of port Pi direction register ...................................................................... 3-33 3.5.3 Structure of port P6 ................................................................................................... 3-34 3.5.4 Structure of port P6 direction register .................................................................... 3-34 3.5.5 Structure of port P9 ................................................................................................... 3-35 3.5.6 Structure of port P9 direction register .................................................................... 3-35 3.5.7 Structure of PWM register (high-order) ................................................................... 3-36 3.5.8 Structure of PWM register (low-order) .................................................................... 3-36 3.5.9 Structure of baud rate generator ............................................................................. 3-37 3.5.10 Structure of UART control register ........................................................................ 3-37 3.5.11 Structure of serial I/O1 automatic transfer data pointer ..................................... 3-38 3.5.12 Structure of serial I/O1 control register 1 ............................................................ 3-38 3.5.13 Structure of serial I/O1 control register 2 ............................................................ 3-39 3.5.14 Structure of serial I/O1 register/Transfer counter ................................................ 3-40 3.5.15 Structure of serial I/O1 control register 3 ............................................................ 3-41 3.5.16 Structure of serial I/O2 control register ................................................................ 3-42 3.5.17 Structure of serial I/O2 status register ................................................................. 3-43 3.5.18 Structure of serial I/O2 transmit/receive buffer register ..................................... 3-43 3.5.19 Structure of timer i ................................................................................................... 3-44 3.5.20 Structure of timer 2 ................................................................................................. 3-44 3.5.21 Structure of PWM control register ......................................................................... 3-44 3.5.22 Structure of timer 6 PWM register ........................................................................ 3-45 3.5.23 Structure of timer 12 mode register ...................................................................... 3-45 3.5.24 Structure of timer 34 mode register ...................................................................... 3-46 3.5.25 Structure of timer 56 mode register ...................................................................... 3-46 3.5.26 Structure of watchdog timer control register ........................................................ 3-47 3.5.27 Structure of timer X (low-order, high-order) ......................................................... 3-47 3.5.28 Structure of timer X mode register 1 .................................................................... 3-48 3.5.29 Structure of timer X mode register 2 .................................................................... 3-49 3.5.30 Structure of interrupt interval determination register .......................................... 3-49 3.5.31 Structure of interrupt interval determination control register ............................. 3-50 3.5.32 Structure of A-D control register ............................................................................ 3-50 3.5.33 Structure of A-D conversion register (low-order) ................................................. 3-51 3.5.34 Structure of A-D conversion register (high-order) ............................................... 3-51 3.5.35 Structure of interrupt source switch register ........................................................ 3-52 3.5.36 Structure of interrupt edge selection register ...................................................... 3-52 3.5.37 Structure of CPU mode register ............................................................................ 3-53 3.5.38 Structure of interrupt request register 1 ............................................................... 3-54
38B5 Group User's Manual
vii
List of figures
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.5.39 Structure of interrupt request register 2 ............................................................... 3-55 3.5.40 Structure of interrupt control register 1 ................................................................ 3-56 3.5.41 Structure of interrupt control register 2 ................................................................ 3-57 3.5.42 Structure of pull-up control register 1 ................................................................... 3-58 3.5.43 Structure of pull-up control register 2 ................................................................... 3-58 3.5.44 Structure of P1FLDRAM write disable register .................................................... 3-59 3.5.45 Structure of P3FLDRAM write disable register .................................................... 3-60 3.5.46 Structure of FLDC mode register .......................................................................... 3-61 3.5.47 Structure of Tdisp time set register ...................................................................... 3-62 3.5.48 Structure of Toff1 time set register ....................................................................... 3-63 3.5.49 Structure of Toff2 time set register ....................................................................... 3-63 3.5.50 Structure of FLD data pointer/FLD data pointer reload register ....................... 3-64 3.5.51 Structure of port P0FLD/Port switch register ....................................................... 3-64 3.5.52 Structure of port P2FLD/port switch register ....................................................... 3-65 3.5.53 Structure of port P8FLD/port switch register ....................................................... 3-65 3.5.54 Structure of port P8FLD output control register .................................................. 3-66 3.5.55 Structure of buzzer output control register........................................................... 3-66 3.12.1 Pin configuration of M35501FP .............................................................................. 3-91 3.12.2 Functional block diagram ........................................................................................ 3-92 3.12.3 Port block diagram ................................................................................................... 3-93 3.12.4 Digit setting ............................................................................................................... 3-94 3.12.5 16-digit mode output waveform .............................................................................. 3-95 3.12.6 Optional digit mode output waveform ................................................................... 3-95 3.12.7 Cascade mode connection example: 17 digits or more selected ..................... 3-96 3.12.8 Cascade mode output waveform ........................................................................... 3-96 3.12.9 Connection example with 38B5 Group microcomputer (1 to 16 digits) ........... 3-97 3.12.10 Connection example with 38B5 Group microccomputer (17 to 32 digits) ..... 3-97 3.12.11 Digit output waveform when reset signal is input ............................................. 3-98 3.12.12 Power-on reset circuit ........................................................................................... 3-99 3.12.13 Timing diagram ..................................................................................................... 3-102
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38B5 Group User's Manual
List of tables
List of tables
CHAPTER 1 HARDWARE
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 1 Pin description (1) ........................................................................................................... 1-4 2 Pin description (2) ........................................................................................................... 1-5 3 List of supported products ............................................................................................. 1-7 4 Push and pop instructions of accumulator or processor status register ................. 1-9 5 Set and clear instructions of each bit of processor status register ....................... 1-10 6 List of I/O port functions (1) ........................................................................................ 1-15 7 List of I/O port functions (2) ........................................................................................ 1-16 8 Interrupt vector addresses and priority ...................................................................... 1-21 9 Pins in FLD automatic display mode .......................................................................... 1-42 10 Relationship between low-order 6-bit data and setting period of ADD bit ......... 1-54 11 Special programming adapter .................................................................................... 1-66 12 Mask option type of pull-down resistor .................................................................... 1-67 13 Interrupt sources, vector addresses and interrupt priority ..................................... 1-69 14 Relative formula for a refernece voltage VREF of A-D converter and Vref ..................... 1-71 15 Change of A-D conversion register during A-D conversion .................................. 1-71
CHAPTER 2 APPLICATION
Table 2.1.1 Termination of unused pins ..................................................................................... 2-6 Table 2.3.1 Setting examples of baud rate generator values and transfer bit rate values ........................................................................................................................................................ 2-73 Table 2.4.1 FLD automatic display RAM map ......................................................................... 2-96 Table 2.4.2 FLD automatic display RAM map example ......................................................... 2-97 Table 2.4.3 FLD automatic display RAM map ....................................................................... 2-104 Table 2.4.4 FLD automatic display RAM map example ....................................................... 2-105 Table 2.4.5 FLD automatic display RAM map example ....................................................... 2-110 Table 2.4.6 FLD automatic display RAM map ....................................................................... 2-116
CHAPTER 3 APPENDIX
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 3.1.1 Absolute maximum ratings ....................................................................................... 3-2 3.1.2 Recommended operating conditions (1) ................................................................ 3-3 3.1.3 Recommended operating conditions (2) ................................................................ 3-4 3.1.4 Electrical characteristics (1)..................................................................................... 3-4 3.1.5 Electrical characteristics (2)..................................................................................... 3-5 3.1.6 A-D converter characteristics .................................................................................. 3-5 3.1.7 Timing requirements ................................................................................................. 3-6 3.1.8 Switching characteristics .......................................................................................... 3-6 3.3.1 Programming adapter ............................................................................................. 3-24 3.3.2 PROM programmer address setting ..................................................................... 3-24 3.12.1 Pin description ....................................................................................................... 3-92 3.12.2 Absolute maximum ratings ................................................................................. 3-100 3.12.3 Recommended operating conditions ................................................................. 3-100 3.12.4 Recommended operating conditions ................................................................. 3-100 3.12.5 Electrical characteristics ..................................................................................... 3-101 3.12.6 Timing requirements ........................................................................................... 3-102
38B5 Group User's Manual
i
CHAPTER 1 HARDWARE
DESCRIPTION FEATURES APPLICATION PIN CONFIGURATION FUNCTIONAL BLOCK PIN DESCRIPTION PART NUMBERING GROUP EXPANSION FUNCTIONAL DESCRIPTION NOTES ON PROGRAMMING NOTES ON USE DATA REQUIRED FOR MASK ORDERS DATA REQUIRED FOR ROM WRITING ORDERS ROM PROGRAMMING METHOD MASK OPTION OF PULL-DOWN RESISTOR FUNCTIONAL DESCRIPTION SUPPLEMENT
HARDWARE
DESCRIPTION/FEATURES/APPLICATION/PIN CONFIGURATION
DESCRIPTION
The 38B5 group is the 8-bit microcomputer based on the 740 family core technology. The 38B5 group has six 8-bit timers, a 16-bit timer, a fluorescent display automatic display circuit, 12-channel 10-bit A-D converter, a serial I/O with automatic transfer function, which are available for controllin g mu sical in str um ent s and hous ehold appli a n c e s . The 38B5 group has variations of internal memory size and packaging. For details, refer to the section on part numbering. For details on availability of microcomputers in the 38B5 group, refer to the section on group expansion. Built-in pull-down resistors connected to high-breakdown voltage ports are available by specifying with the mask option in some products. For the details, refer to the section on the mask option of pull-down resistor.
* * * * * * * *
*
FEATURES
* * * * * * * * *
Basic machine-language instructions ....................................... 71 The minimum instruction execution time .......................... 0.48 s (at 4.19 MHz oscillation frequency) Memory size ROM ............................................. 24K to 60K bytes RAM .......................................... 1024 to 2048 bytes Programmable input/output ports ............................................. 55 High-breakdown-voltage output ports ...................................... 36 Software pull-up resistors ....... (Ports P5, P61 to P65, P7, P84 to P87, P9) Interrupts .................................................. 21 sources, 16 vectors Timers ........................................................... 8-bit ! 6, 16-bit ! 1 Serial I/O1 (Clock-synchronized) ................................... 8-bit ! 1 ...................... (max. 256-byte automatic transfer function)
*
*
Serial I/O2 (UART or Clock-synchronized) .................... 8-bit ! 1 PWM ............................................................................ 14-bit ! 1 8-bit ! 1 (also functions as timer 6) A-D converter .............................................. 10-bit ! 12 channels Fluorescent display function ......................... Total 40 control pins Interrupt interval determination function ..................................... 1 Watchdog timer ............................................................ 20-bit ! 1 Buzzer output ............................................................................. 1 2 Clock generating circuit Main clock (XIN-XOUT) .......................... Internal feedback resistor Sub-clock (XCIN-XCOUT) .......... Without internal feedback resistor (connect to external ceramic resonator or quartz-crystal oscillator) Power source voltage In high-speed mode ................................................... 4.0 to 5.5 V (at 4.19 MHz oscillation frequency and high-speed selected) In middle-speed mode ................................................ 2.7 to 5.5 V (at 4.19 MHz oscillation frequency and middle-speed selected) In low-speed mode ..................................................... 2.7 to 5.5 V (at 32 kHz oscillation frequency) Power dissipation In high-speed mode .......................................................... 35 mW (at 4.19 MHz oscillation frequency) In low-speed mode ............................................................. 60 W (at 32 kHz oscillation frequency, at 3 V power source voltage) Operating temperature range ................................... -20 to 85 C
APPLICATION
Musical instruments, VCR, household appliances, etc.
PIN CONFIGURATION (TOP VIEW)
P20/BUZ02/FLD0 P21/FLD1 P22/FLD2 P23/FLD3 P24/FLD4 P25/FLD5 P26/FLD6 P27/FLD7 P00/FLD8 P01/FLD9 P02/FLD10 P03/FLD11 P04/FLD12 P05/FLD13 P06/FLD14 P07/FLD15 P10/FLD16 P11/FLD17 P12/FLD18 P13/FLD19 P14/FLD20 P15/FLD21 P16/FLD22 P17/FLD23
56 54 52 58 64 60 62 57 55 53 51 49 47 45 43 63 59 61 50 48 46 44 42 41
P57/SRDY2/SCLK22 P56/SCLK21 P55/TxD P54/RxD P53/SCLK12 P52/SCLK11 P51/SOUT1 P50/SIN1 AVSS VREF P65/SSTB1/AN11 P64/INT4/SBUSY1/AN10 P63/AN9 P62/SRDY1/AN8 P77/AN7 P76/AN6
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
2 4 5 6 1 3 7 8 9 10 13 15 17 19 21 11 12 14 16 18 20 22 23 24
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
M38B5xMxH-XXXXFP
P30/FLD24 P31/FLD25 P32/FLD26 P33/FLD27 P34/FLD28 P35/FLD29 P36/FLD30 P37/FLD31 P80/FLD32 P81/FLD33 P82/FLD34 P83/FLD35 VEE P84/FLD36 P85/RTP0/FLD37 P86/RTP1/FLD38
Fig. 1 Pin configuration of M38B5xMxH-XXXXFP
1-2
P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 P61/CNTR0/CNTR2 (Note) P60/CNTR1 P47/INT2 RESET P91/XCOUT P90/XCIN Vss XIN XOUT Vcc P46/T3OUT P45/T1OUT P44/PWM1 P43/BUZ01 (Note) P42/INT3 P41/INT1 P40/INT0 P87/PWM0/FLD39
Note: In the mask option type P, INT3 and CNTR1 cannot be used.
Package type : 80P6N-A 80-pin plastic-molded QFP
38B5 Group User's Manual
FUNCTIONAL BLOCK DIAGRAM (Package : 80P6N-A)
I/O ports
Port P1(8) Port P2(8) Port P3(8) Port P4(8)
8 8 8 8
1
7
FUNCTIONAL BLOCK
Fig. 2 Functional block diagram
Port P0(8)
Build-in peripheral functions
Timers System clock generation
A-D converter
(10-bit ! 12 channel)
Serial I/O
XIN-XOUT (main-clock) XCIN-XCOUT (sub-clock)
Serial I/O1(Clock-synchronized) (256 byte automatic transfer)
Serial I/O2 (Clock-synchronized or UART)
Timer X(16-bit) Timer 1(8-bit) Timer 2(8-bit) Timer 3(8-bit) Timer 4(8-bit) Timer 5(8-bit) Timer 6(8-bit)
PWM1(8-bit)
Memory CPU core
ROM
38B5 Group User's Manual
PWM0(14-bit)
Buzzer output Watchdog timer RAM Interrupt interval determination function
FLD display function
40 control pins
(36 high-breakdown voltage ports)
Port P5(8) 6
Port P6(6)
Port P7(8) 8
Port P8(8) 8
Port P9(2) 2
FUNCTIONAL BLOCK
HARDWARE
8
1-3
HARDWARE
PIN DESCRIPTION
PIN DESCRIPTION
Table 1 Pin description (1) Pin VCC, VSS VEE VREF AVSS
______
Name Power source Pull-down power source Reference voltage Analog power source Reset input Clock input
Function * Apply voltage of 4.0-5.5 V to VCC, and 0 V to VSS. * Apply voltage supplied to pull-down resistors of ports P0, P1, and P3. * Reference voltage input pin for A-D converter. * Analog power source input pin for A-D converter. * Connect to VSS. * Reset input pin for active "L." * Input and output pins for the main clock generating circuit. * Feedback resistor is built in between XIN pin and XOUT pin.
Function except a port function
RESET XIN
XOUT
Clock output
P00/FLD8- P07/FLD15
I/O port P0
* Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. * When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. * The clock is used as the oscillating source of system clock. * 8-bit I/O port. * FLD automatic display * I/O direction register allows each pin to be individually programmed as either pins input or output. * At reset, this port is set to input mode. * A pull-down resistor is built in between port P0 and the VEE pin. * CMOS compatible input level. * High-breakdown-voltage P-channel open-drain output structure.
P10/FLD16- Output port P1 P17/FLD23
* At reset, this port is set to VEE level. * 8-bit output port. * A pull-down resistor is built in between port P1 and the VEE pin. * High-breakdown-voltage P-channel open-drain output structure. * At reset, this port is set to VEE level. * 8-bit I/O port with the same function as port P0. * Low-voltage input level. * High-breakdown-voltage P-channel open-drain output structure. * 8-bit output port. * A pull-down resistor is built in between port P3 and the VEE pin. * High-breakdown-voltage P-channel open-drain output structure. * At reset, this port is set to VEE level. * 7-bit I/O port with the same function as port P0. * CMOS compatible input level * N-channel open-drain output structure.
* FLD automatic display pins
P20/BUZ02/ I/O port P2 FLD0- P27/FLD7 P30/FLD24- Output port P3 P37/FLD31
* FLD automatic display pins * Buzzer output pin (P20) * FLD automatic display pins
P40/INT0, P41/INT1, P42/INT3 P43/BUZ01 P44/PWM1 P45/T1OUT, P46/T3OUT P47/INT2
I/O port P4
* Interrupt input pins In the mask option type P, INT3 cannot be used. * Buzzer output pin * PWM output pin (Timer output pin) * Timer output pin * Interrupt input pin
Input port P4
* 1-bit input port. * CMOS compatible input level.
1-4
38B5 Group User's Manual
HARDWARE
PIN DESCRIPTION
Table 2 Pin description (2) Pin P50/SIN1, P51/SOUT1, P52/SCLK11, P53/SCLK12 P54/RXD, P55/TXD, P56/SCLK21, P57/SRDY2/ SCLK22 P60/CNTR1 I/O port P6 * 1-bit I/O port with the same function as port P0. * CMOS compatible input level. * N-channel open-drain output structure. P61/CNTR0/ CNTR2 P62/SRDY1/ AN8 P63/AN9 P64/INT4/ SBUSY1/AN10, P65/SSTB1/ AN11 P70/AN0- P77/AN7 P80/FLD32- I/O port P8 P83/FLD35 P84/FLD36 P85/RTP0/ FLD37, P86/RTP1/ FLD38 P87/PWM0/ FLD39 P90/XCIN, P91/XCOUT I/O port P9 * 2-bit CMOS I/O port with the same function as port P0. * CMOS compatible input level. * CMOS 3-state output structure. I/O port P7 * 8-bit CMOS I/O port with the same function as port P0. * CMOS compatible input level. * CMOS 3-state output structure. * 4-bit I/O port with the same function as port P0. * Low-voltage input level. * High-breakdown-voltage P-channel open-drain output structure. * 4-bit CMOS I/O port with the same function as port P0. * Low-voltage input level. * CMOS 3-state output structure * FLD automatic display pins * Real time port output * FLD automatic display pins * 5-bit CMOS I/O port with the same function as port P0. * CMOS compatible input level. * CMOS 3-state output structure. * Serial I/O1 function pin * A-D conversion input pin * A-D conversion input pin * Dimmer signal output pin * Serial I/O1 function pin * A-D conversion input pin * Interrupt input pin (P64) * A-D conversion input pin * Timer input pin In the mask option type P, CNTR1 cannot be used. * Timer I/O pin * Serial I/O2 function pins Name I/O port P5 * CMOS compatible input level. * CMOS 3-state output structure. Function * 8-bit CMOS I/O port with the same function as port P0. Function except a port function * Serial I/O1 function pins
* FLD automatic display pins * 14-bit PWM output * I/O pins for sub-clock generating
circuit (connect a ceramic resonator or a quarts-crystal oscillator)
38B5 Group User's Manual
1-5
HARDWARE
PART NUMBERING
PART NUMBERING
Product M38B5 7 M C H - XXXX FP
Package type FP : 80P6N-A package FS : 80D0 package ROM number Omitted in One Time PROM version shipped in blank and EPROM version. 3 digits for M38B57M6-XXXFP and One Time PROM version. High-breakdown voltage pull-down option Regarding option contents, refer to section " MASK OPTION OF PULL-DOWN RESISTOR". For the M38B57M6-XXXFP, One Time PROM version, and EPROM version, there is not the option specification. ROM/PROM size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes 9 : 36864 bytes A : 40960 bytes B : 45056 bytes C : 49152 bytes D : 53248 bytes E : 57344 bytes F : 61440 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used for users. Memory type M : Mask ROM version E : EPROM or One Time PROM version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes
Fig. 3 Part numbering
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38B5 Group User's Manual
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GROUP EXPANSION
GROUP EXPANSION
Mitsubishi plans to expand the 38B5 group as follows:
Memory Type
Support for Mask ROM, One Time PROM and EPROM versions.
Memory Size
ROM/PROM size .................................................. 24K to 60K bytes RAM size ............................................................ 1024 to 2048 bytes
Package
80P6N-A ..................................... 0.8 mm-pitch plastic molded QFP 80D0 ........................ 0.8 mm-pitch ceramic LCC (EPROM version)
Mass product
ROM size (bytes) 60K 56K 52K 48K 44K 40K 36K 32K 28K 24K 20K 16K 12K 8K 4K
256 512 768 1,024 1,536 Mass product M38B57M6 Mass product M38B57MCH
M38B59EF M38B59MFH New product
2,048
RAM size (bytes)
Note : Products under development or planning : the development schedule and specifications may be revised without notice. Fig. 4 Memory expansion plan Currently supported products are listed below. Table 3 List of supported products (P) ROM size (bytes) Product ROM size for User ( ) 24576 M38B57M6-XXXFP (24446) 49152 M38B57MCH-XXXXFP (49022) 61440 M38B59MFH-XXXXFP (61310) 61440 M38B59EF-XXXFP (61310) 61440 M38B59EFFP (61310) 61440 M38B59EFFS (61310) As of Nov. 1998 RAM size (bytes) 1024 1024 2048 2048 2048 2048 Package 80P6N-A 80P6N-A 80P6N-A 80P6N-A 80P6N-A 80D0 Remarks Mask ROM version Corresponded to mask option Mask ROM version Mask ROM version Corresponded to mask option One Time PROM version One Time PROM version (blank) EPROM version
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HARDWARE
FUNCTIONAL DESCRIPTION
FUNCTIONAL DESCRIPTION Central Processing Unit (CPU)
The 38B5 group uses the standard 740 Family instruction set. Refer to the table of 740 Series addressing modes and machine instructions or the 740 Series Software Manual for details on the instruction set. Machine-resident 740 Series instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used.
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is "0" , the high-order 8 bits becomes "0016". If the stack page selection bit is "1", the high-order 8 bits becomes "0116". The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 6. Store registers other than those described in Figure 6 with program when the user needs them during interrupts or subroutine calls.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address.
b7 A b7 X b7 Y b7 S b15 PCH b7 b7 PCL
b0 Accumulator b0 Index register X b0 Index register Y b0 Stack pointer b0 Program counter b0 Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag
NVTBD I ZC
Fig. 5 740 Family CPU register structure
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FUNCTIONAL DESCRIPTION
On-going Routine
Interrupt request (Note) Execute JSR M (S) Push return address on stack (S) M (S) (S) (PCH) (S) - 1 (PCL) (S)- 1
M (S) (S) M (S) (S) M (S) (S)
(PCH) (S) - 1 (PCL) (S) - 1 (PS) (S) - 1 Push contents of processor status register on stack Push return address on stack
Subroutine Execute RTS POP return address from stack (S) (PCL) (S) (PCH) (S) + 1 M (S) (S) + 1 M (S)
Interrupt Service Routine
Execute RTI (S) (PS) (S) (PCL) (S) (PCH) (S) + 1 M (S) (S) + 1 M (S) (S) + 1 M (S)
I Flag is set from "0" to "1" Fetch the jump vector POP contents of processor status register from stack
POP return address from stack
Note: Condition for acceptance of an interrupt
Interrupt enable flag is "1" Interrupt disable flag is "0"
Fig. 6 Register push and pop at interrupt generation and subroutine call
Table 4 Push and pop instructions of accumulator or processor status register Push instruction to stack Accumulator Processor status register PHA PHP Pop instruction from stack PLA PLP
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HARDWARE
FUNCTIONAL DESCRIPTION
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. *Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. *Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is "0", and cleared if the result is anything other than "0". *Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is "1". *Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is "0"; decimal arithmetic is executed when it is "1". Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic. *Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always "0". When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to "1". *Bit 5: Index X mode flag (T) When the T flag is "0", arithmetic operations are performed between accumulator and memory. When the T flag is "1", direct arithmetic operations and direct data transfers are enabled between memory locations. *Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. *Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag.
Table 5 Set and clear instructions of each bit of processor status register C flag Set instruction Clear instruction SEC CLC Z flag _ _ I flag SEI CLI D flag SED CLD B flag _ _ T flag SET CLT V flag _ CLV N flag _ _
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FUNCTIONAL DESCRIPTION
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and the internal system clock selection bit etc. The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM: address 003B16)
Processor mode bits b1 b0 0 0 : Single-chip mode 0 1: 1 0 : Not available 1 1: Stack page selection bit 0: Page 0 1: Page 1 XCOUT drivability selection bit 0: Low drive 1: High drive Port XC switch bit 0: I/O port function 1: XCIN-XCOUT oscillating function Main clock (XIN-XOUT) stop bit 0: Oscillating 1: Stopped Main clock division ratio selection bit 0: f(XIN) (high-speed mode) 1: f(XIN)/4 (middle-speed mode) Internal system clock selection bit 0: XIN-XOUT selection (middle-/high-speed mode) 1: XCIN-XCOUT selection (low-speed mode)
Fig. 7 Structure of CPU mode register
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HARDWARE
FUNCTIONAL DESCRIPTION
Memory Special function register (SFR) area
The special function register (SFR) area in the zero page contains control registers such as I/O ports and timers.
Zero page
The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode.
RAM
RAM is used for data storage and for stack area of subroutine calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for device testing, and the other areas are user areas for storing programs.
Special page
The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
RAM area
RAM size (byte) Address XXXX16
000016 RAM 004016 010016 SFR area 1 Zero page
192 256 384 512 640 768 896 1024 1536 2048 ROM area
ROM size (byte)
00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 063F16 083F16
XXXX16 Reserved area 044016 Not used (Note)
Address ZZZZ16
Address YYYY16
0EF016 0EFF16 0F0016 ROM 0FFF16 YYYY16
SFR area 2
RAM area for Serial I/O automatic transfer RAM area for FLD automatic display
4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440
F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016
F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016
Reserved ROM area
(common ROM area,128 byte)
ZZZZ16
FF0016
FFDC16 FFFE16 FFFF16
Special page Interrupt vector area Reserved ROM area
Note: When 1024 bytes or more are used as RAM area, this area can be used.
Fig. 8 Memory map diagram
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FUNCTIONAL DESCRIPTION
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 0EF016 0EF116 0EF216 0EF316 0EF416 0EF516 0EF616 0EF716
Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1)
002016 002116 002216 002316
Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer 4 (T4) Timer 5 (T5) Timer 6 (T6) PWM control register (PWMCON) Timer 6 PWM register (T6PWM) Timer 12 mode register (T12M) Timer 34 mode register (T34M) Timer 56 mode register (T56M) Watchdog timer control register (WDTCON) Timer X (low-order) (TXL) Timer X (high-order) (TXH) Timer X mode register 1 (TXM1) Timer X mode register 2 (TXM2) Interrupt interval determination register (IID)
Interrupt interval determination control register (IIDCON)
Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3)
002416 002516 002616 002716
Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) Port P7 (P7) Port P7 direction register (P7D) Port P8 (P8) Port P8 direction register (P8D) Port P9 (P9) Port P9 direction register (P9D) PWM register (high-order) (PWMH) PWM register (low-order) (PWM L) Baud rate generator (BRG) UART control register (UARTCON)
Serial I/O1 automatic transfer data pointer (SIO1DP)
002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 0EF816 0EF916 0EFA16 0EFB16
A-D control register (ADCON) A-D conversion register (low-order) (ADL) A-D conversion register (high-order) (ADH)
Serial I/O1 control register 1 (SIO1CON1) Serial I/O1 control register 2 (SIO1CON2) Serial I/O1 register/Transfer counter (SIO1) Serial I/O1 control register 3 (SIO1CON3) Serial I/O2 control register (SIO2CON) Serial I/O2 status register (SIO2STS)
Serial I/O2 transmit/receive buffer register (TB/RB)
Interrupt source switch register (IFR) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1(IREQ1) Interrupt request register 2(IREQ2) Interrupt control register 1(ICON1) Interrupt control register 2(ICON2) FLD data pointer (FLDDP) Port P0FLD/port switch register (P0FPR) Port P2FLD/port switch register (P2FPR) Port P8FLD/port switch register (P8FPR)
Pull-up control register 1 (PULL1) Pull-up control register 2 (PULL2)
P1FLDRAM write disable register (P1FLDRAM) P3FLDRAM write disable register (P3FLDRAM)
FLDC mode register (FLDM) Tdisp time set register (TDISP) Toff1 time set register (TOFF1) Toff2 time set register (TOFF2)
0EFC16 Port P8FLD output control register (P8FLDCON) 0EFD16 Buzzer output control register (BUZCON) 0EFE16 0EFF16
Fig. 9 Memory map of special function register (SFR)
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HARDWARE
FUNCTIONAL DESCRIPTION
I/O Ports [Direction Registers] PiD
The 38B5 group has 55 programmable I/O pins arranged in eight individual I/O ports (P0, P2, P40-P46, and P5-P9). The I/O ports have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. When "0" is written to the bit corresponding to a pin, that pin becomes an input pin. When "1" is written to that pin, that pin becomes an output pin. If data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input (the bit corresponding to that pin must be set to "0") are floating and the value of that pin can be read. If a pin set to input is written to, only the port output latch is written to and the pin remains floating.
b7 b0 Pull-up control register 1 (PULL1 : address 0EF0 16) P50, P51 pull-up control bit P52, P53 pull-up control bit P54, P55 pull-up control bit P56, P57 pull-up control bit P61 pull-up control bit P62, P63 pull-up control bit P64, P65 pull-up control bit Not used (returns "0" when read) 0: No pull-up 1: Pull-up
[High-Breakdown-Voltage Output Ports]
The 38B5 group has 5 ports with high-breakdown-voltage pins (ports P0-P3 and P80-P83). The high-breakdown-voltage ports have Pchannel open-drain output with Vcc- 45 V of breakdown voltage. Each pin in ports P0, P1, and P3 has an internal pull-down resistor connected to VEE. At reset, the P-channel output transistor of each port latch is turned off, so that it goes to VEE level ("L") by the pull-down resistor. Writing "1" (weak drivability) to bit 7 of the FLDC mode register (address 0EF416) shows the rising transition of the output transistors for reducing transient noise. At reset, bit 7 of the FLDC mode register is set to "0" (strong drivability).
b7 b0 Pull-up control register 2 (PULL2 : address 0EF1 16) P70, P71 pull-up control bit P72, P73 pull-up control bit P74, P75 pull-up control bit P76, P77 pull-up control bit P84, P85 pull-up control bit P86, P87 pull-up control bit P90, P91 pull-up control bit Not used (returns "0" when read) 0: No pull-up 1: Pull-up
[Pull-up Control Register] PULL
Ports P5, P61-P65, P7, P84-P87 and P9 have built-in programmable pull-up resistors. The pull-up resistors are valid only in the case that the each control bit is set to "1" and the corresponding port direction registers are set to input mode.
Fig. 10 Structure of pull-up control registers (PULL1 and PULL2)
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FUNCTIONAL DESCRIPTION
Table 6 List of I/O port functions (1) Pin P00/FLD8- P07/FLD15 Name Port P0 Input/Output Input/output, individual bits I/O Format Non-Port Function Related SFRs Ref.No. (1)
CMOS compatible input level FLD automatic display function FLDC mode register High-breakdown voltage PPort P0FLD/port switch register channel open-drain output with pull-down resistor
P10/FLD16- Port P1 P17/FLD23 P20/BUZ02/ FLD0 P21/FLD1- P27/FLD7 P30/FLD24- Port P3 P37/FLD31 P40/INT0, P41/INT1, P42/INT3 P43/BUZ01 P44/PWM1 P45/T1OUT P46/T3OUT P47/INT2 Port P4 Port P2
Output
High-breakdown voltage Pchannel open-drain output with pull-down resistor Low-voltage input level High-breakdown voltage Pchannel open-drain output
FLDC mode register
(2)
Input/output, individual bits
Buzzer output (P20)
FLDC mode register
(3) (1) (2)
FLD automatic display function Port P2FLD/port switch register FLD automatic display function Buzzer output control register FLDC mode register
Output
High-breakdown voltage Pchannel open-drain output with pull-down resistor
Input/output, individual bits
CMOS compatible input level External interrupt input N-channel open-drain output In the mask option type P, INT3 cannot be used. Buzzer output PWM output Timer output Timer output
Interrupt edge selection register
(5-1) (5-2)
Buzzer output control register Timer 56 mode register Timer 12 mode register Timer 34 mode register Interrupt edge selection register Interrupt interval determination control register
(4) (6) (7) (7) (8)
Input
CMOS compatible input level External interrput input
P50/SIN1 P51/SOUT1, P52/SCLK11, P53/SCLK12 P54/RXD, P55/TXD, P56/SCLK21 P57/SRDY2/ SCLK22
Port P5
Input/output, individual bits
CMOS compatible input level Serial I/O1 function I/O CMOS 3-state output
Serial I/O1 control register 1, 2
(9) (10)
Serial I/O2 function I/O
Serial I/O2 control register UART control register
(9) (10) (11)
P60/CNTR1 Port P6 P61/CNTR0/ CNTR2 P62/SRDY1/ AN8 P63/AN9 P64/INT4/ SBUSY1/AN10 P65/SSTB1/ AN11 P70/AN0- P77/AN7 Port P7
CMOS compatible input level External count input N-channel open-drain output In the mask option type P, CMOS compatible input level CNTR1 cannot be used. CMOS 3-state output Serial I/O1 function I/O A-D conversion input A-D conversion input Dimmer signal output Serial I/O1 function I/O A-D conversion input External interrupt input Serial I/O1 function I/O A-D conversion input A-D conversion input
Interrupt edge selection register
(5-1) (5-2) (12) (13) (14) (15)
Serial I/O1 control register 1, 2 A-D control register A-D control register P8FLD output control bit Serial I/O1 control register 1, 2 A-D control register Interrupt edge selection register Serial I/O1 control register 1, 2 A-D control register A-D control register
(16) (14)
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HARDWARE
FUNCTIONAL DESCRIPTION
Table 7 List of I/O port functions (2) Pin P83/FLD35 P84/FLD36 P85/RTP0/ FLD37, P86/RTP1/ FLD38 P87/PWM0/ FLD39 P90/XCIN P91/XCOUT Port P9 Name Input/Output Input/output, individual bits I/O Format Low-voltage input level High-breakdown voltage Pchannel open-drain output Low-voltage input level CMOS 3-state output Non-Port Function Related SFRs Port P8FLD/port switch register (17) (18) Ref.No. (1)
P80/FLD32- Port P8
FLD automatic display function FLDC mode register
FLD automatic display function FLDC mode register Real time port output Port P8FLD/port switch register Timer X mode register 2
FLD automatic display function FLDC mode register PWM output Port P8FLD/port switch register PWM control register CMOS compatible input level Sub-clock generating circuit I/O CPU mode register CMOS 3-state output
(19)
(20) (21)
Notes 1 : How to use double-function ports as function I/O ports, refer to the applicable sections. 2 : Make sure that the input level at each pin is either 0 V or Vcc during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from Vcc to Vss through the input-stage gate.
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FUNCTIONAL DESCRIPTION
(1) Ports P0, P21-P27, P80-P83
FLD/Port switch register
(2) Ports P1, P3
Dimmer signal (Note 1)
Local data bus Data bus
Direction register Port latch
Local data bus
Dimmer signal (Note 1) Port latch
*
read
Data bus
*
VEE
(Note 2) VEE
(3) Port P20
FLD/Port switch register Dimmer signal (Note 1) Buzzer control signal Buzzer signal output
(4) Port P43
Buzzer control signal Buzzer signal output
Direction register
Local data bus Data bus
Direction register
Data bus
Port latch
Port latch
*
read
(Note 2) VEE
(5-1) Ports P40-P42, P60
(5-2) Ports P42, P60 (in mask option type P)
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
INT0,INT1,INT3 interrupt input CNTR1 input Timer 4 external clock input
(6) Port P44
Timer 6 output selection bit
Direction register
(7) Ports P45, P46
Timer 1 output bit Timer 3 output bit
Direction register
Data bus
Port latch
Data bus
Port latch
Timer 1 output Timer 3 output Timer 6 output
(Note 3)
* High-breakdown-voltage P-channel transistor Notes 1: The dimmer signal sets the Toff timing. 2: A pull-down resistor is not built in to ports P2 and P8. 3: In the mask option type P, the hysteresis circuit of part is not built-in.
Fig. 11 Port block diagram (1)
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HARDWARE
FUNCTIONAL DESCRIPTION
(8) Port P47
(9) Ports P50, P54
Data bus
Pull-up control
INT2 interrupt input Data bus
Direction register
Port latch
Serial I/O input
(10) Ports P51-P53, P55, P56
Pull-up control P-channel output disable signal (P51,P55) Output OFF control signal Serial I/O2 mode selection bit
Direction register
(11) Port P57
Pull-up control SRDY2 output enable bit
Direction register
Data bus
Port latch
Data bus
Port latch
TXD, SOUT or SCLK Serial clock input P52,P53,P56
Serial ready output Serial clock input
(12) Port P61
(13) Port P62
Pull-up control P62/SRDY1*P64/SBUSY1 pin control bit
Direction register
Pull-up control Timer X operating mode bit
Direction register
Data bus
Port latch
Data bus
Port latch
Timer X output CNTR0,CNTR2 input Timer 2, Timer X external clock input
Serial ready output Serial ready input A-D conversion input Analog input pin selection bit
Fig. 12 Port block diagram (2)
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FUNCTIONAL DESCRIPTION
(14) Ports P63, P7
Pull-up control Dimmer output control bit (P63)
Direction register
(15) Port P64
Pull-up control P62/SRDY1*P64/SBUSY1 pin control bit
Direction register
Data bus Data bus
Port latch
Port latch
SBUSY1 output INT4 interrupt input, SBUSY1 input Dimmer signal output (P63) A-D conversion input Analog input pin selection bit A-D conversion input
Analog input pin selection bit
(16) Port P65
Pull-up control P65/SSTB1 pin control bit
Direction register
(17) Port P84
Dimmer signal (Note)
Pull-up control
FLD/Port switch register
Data bus
Port latch
Direction register
Local data bus Data bus
Port latch
SSTB1 output A-D conversion input
(18) Ports P85, P86
Dimmer signal (Note) FLD/Port switch register Real time port control bit Direction register
(19) Port P87
Pull-up control
Dimmer signal (Note)
Pull-up control
P87/PWM output enable bit
FLD/Port switch register
Local data bus Data bus
Port latch
Local data bus Data bus
Direction register
Port latch
RTP output
PWM0 output
(20) Port P90
Pull-up control
(21) Port P91
Pull-up control Port Xc switch bit
Direction register
Port Xc switch bit
Direction register
Data bus
Port latch
Data bus
Port latch
Oscillator Port P90 Sub-clock generating circuit input Port Xc switch bit * High-breakdown-voltage P-channel transistor Note: The dimmer signal sets the Toff timing.
Fig. 13 Port block diagram (3)
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FUNCTIONAL DESCRIPTION
Interrupts
Interrupts occur by twenty one sources: five external, fifteen internal, and one software.
(1) Interrupt Control
Each interrupt except the BRK instruction interrupt have both an interrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag. An interrupt occurs if the corresponding interrupt request and enable bits are "1" and the interrupt disable flag is "0." Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction interrupt and reset cannot be disabled with any flag or bit. The I flag disables all interrupts except the BRK instruction interrupt and reset. If several interrupts requests occurs at the same time the interrupt with highest priority is accepted first.
(2) Interrupt Operation
Upon acceptance of an interrupt the following operations are automatically performed: 1. The contents of the program counter and processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vector table into the program counter.
sNotes on Use
When the active edge of an external interrupt (INT0-INT4) is set or when switching interrupt sources in the same vector address, the corresponding interrupt request bit may also be set. Therefore, please take following sequence: (1) Disable the external interrupt which is selected. (2) Change the active edge in interrupt edge selection register (3) Clear the set interrupt request bit to "0." (4) Enable the external interrupt which is selected.
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FUNCTIONAL DESCRIPTION
Table 8 Interrupt vector addresses and priority Interrupt Source Priority Reset (Note 2) INT0 INT1 INT2 Remote control/ counter overflow Serial I/O1 Serial I/O automatic transfer Timer X Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 Timer 6 Serial I/O2 receive INT3 Serial I/O2 transmit INT4 6 7 8 9 10 11 12 13 14 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 5 FFF516 FFF416 1 2 3 4 Vector Addresses (Note 1) High FFFD16 FFFB16 FFF916 FFF716 Low FFFC16 FFFA16 FFF816 FFF616 Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At detection of either rising or falling edge of INT2 input At 8-bit counter overflow At completion of data transfer At completion of the last data transfer At timer X underflow At timer 1 underflow At timer 2 underflow At timer 3 underflow At timer 4 underflow At timer 5 underflow At timer 6 underflow At completion of serial I/O2 data receive At detection of either rising or falling edge of INT3 input At completion of serial I/O2 data transmit At detection of either rising or falling edge of INT4 input At completion of A-D conversion 16 FFDF16 FFDE16 Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when interrupt interval determination is operating Valid when serial I/O ordinary mode is selected Valid when serial I/O automatic transfer mode is selected Remarks
STP release timer underflow (Note 3)
External interrupt (Note 4) (active edge selectable) External interrupt (active edge selectable) Valid when INT4 interrupt is selected Valid when A-D conversion is selected
15
FFE116
FFE016
A-D conversion FLD blanking
At falling edge of the last timing immediately Valid when FLD blanking before blanking period starts interrupt is selected FLD digit At rising edge of digit (each timing) Valid when FLD digit interrupt is selected BRK instruction 17 FFDD16 FFDC16 At BRK instruction execution Non-maskable software interrupt Notes 1 : Vector addresses contain interrupt jump destination addresses. 2 : Reset function in the same way as an interrupt with the highest priority. 3 : In the mask option type P, timer 4 interrupt whose count source is CNTR1 input cannot be used. 4 : In the mask option type P, INT3 interrupt cannot be used.
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HARDWARE
FUNCTIONAL DESCRIPTION
Interrupt request bit Interrupt enable bit
Interrupt disable flag I
BRK instruction Reset
Interrupt request
Fig. 14 Interrupt control
b7
b0 Interrupt source switch register (IFR : address 003916) INT3/serial I/O2 transmit interrupt switch bit (Note 1) 0 : INT3 interrupt 1 : Serial I/O2 transmit interrupt INT4/AD conversion interrupt switch bit 0 : INT4 interrupt 1 : A-D conversion interrupt Not used (return "0" when read) (Do not write "1" to these bits.)
b7
b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 interrupt edge selection bit INT1 interrupt edge selection bit 0 : Falling edge active INT2 interrupt edge selection bit 1 : Rising edge active INT3 interrupt edge selection bit (Note 1) INT4 interrupt edge selection bit Not used (return "0" when read) 0 : Rising edge count CNTR0 pin edge switch bit 1 : Falling edge count CNTR1 pin edge switch bit (Note 1)
b7
b0 Interrupt request register 1 (IREQ1 : address 003C16) INT0 interrupt request bit INT1 interrupt request bit INT2 interrupt request bit Remote controller/counter overflow interrupt request bit Serial I/O1 interrupt request bit
Serial I/O automatic transfer interrupt request bit
b7
b0 Interrupt request register 2 (IREQ2 : address 003D16) Timer 4 interrupt request bit (Note 2) Timer 5 interrupt request bit Timer 6 interrupt request bit Serial I/O2 receive interrupt request bit INT3/serial I/O2 transmit interrupt request bit (Note 2) INT4 interrupt request bit AD conversion interrupt request bit FLD blanking interrupt request bit FLD digit interrupt request bit Not used (returns "0" when read) 0 : No interrupt request issued 1 : Interrupt request issued
Timer X interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit
b7
b0 Interrupt control register 1 (ICON1 : address 003E16) INT0 interrupt enable bit INT1 interrupt enable bit INT2 interrupt enable bit Remote controller/counter overflow interrupt enable bit Serial I/O1 interrupt enable bit
Serial I/O automatic transfer interrupt enable bit
b7
b0 Interrupt control register 2 (ICON2 : address 003F16) Timer 4 interrupt enable bit (Note 3) Timer 5 interrupt enable bit Timer 6 interrupt enable bit Serial I/O2 receive interrupt enable bit INT3/serial I/O2 transmit interrupt enable bit (Note 3) INT4 interrupt enable bit AD conversion interrupt enable bit FLD blanking interrupt enable bit FLD digit interrupt enable bit Not used (returns "0" when read) (Do not write "1" to this bit.) 0 : Interrupt disabled 1 : Interrupt enabled
Timer X interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit
Notes 1: In the mask option type P, these bits are not available because CNTR1 function and INT3 function cannot be used. 2: In the mask option type P, if timer 4 interrupt whose count source is CNTR1 input and INT3 interrupt are selected, these bits do not become "1". 3: In the mask option type P, timer 4 interrupt whose count source is CNTR1 input and INT3 interrupt are not available.
Fig. 15 Structure of interrupt related registers
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FUNCTIONAL DESCRIPTION
Timers 8-Bit Timer
The 38B5 group has six built-in timers : Timer 1, Timer 2, Timer 3, Timer 4, Timer 5, and Timer 6. Each timer has the 8-bit timer latch. All timers are down-counters. When the timer reaches "0016," an underflow occurs with the next count pulse. Then the contents of the timer latch is reloaded into the timer and the timer continues down-counting. When a timer underflows, the interrupt request bit corresponding to that timer is set to "1." The count can be stopped by setting the stop bit of each timer to "1." The internal system clock can be set to either the high-speed mode or low-speed mode with the CPU mode register. At the same time, timer internal count source is switched to either f(XIN) or f(XCIN). qTimer 1, Timer 2 The count sources of timer 1 and timer 2 can be selected by setting the timer 12 mode register. A rectangular waveform of timer 1 underflow signal divided by 2 can be output from the P45/T1OUT pin. The active edge of the external clock CNTR0 can be switched with the bit 6 of the interrupt edge selection register. At reset or when executing the STP instruction, all bits of the timer 12 mode register are cleared to "0," timer 1 is set to "FF16," and timer 2 is set to "0116." qTimer 3, Timer 4 The count sources of timer 3 and timer 4 can be selected by setting the timer 34 mode register. A rectangular waveform of timer 3 underflow signal divided by 2 can be output from the P46/T3OUT pin. The active edge of the external clock CNTR1 (Note) can be switched with the bit 7 of the interrupt edge selection register. Note: In the mask option type P, CNTR1 function cannot be used.
b7 b7 b0
Timer 12 mode register (T12M: address 002816) Timer 1 count stop bit 0 : Count operation 1 : Count stop Timer 2 count stop bit 0 : Count operation 1 : Count stop Timer 1 count source selection bits 00 : f(XIN)/8 or f(XCIN)/16 01 : f(XCIN) 10 : f(XIN)/16 or f(XCIN)/32 11 : f(XIN)/64 or f(XCIN)/128 Timer 2 count source selection bits 00 : Underflow of Timer 1 01 : f(XCIN) 10 : External count input CNTR0 11 : Not available Timer 1 output selection bit (P45) 0 : I/O port 1 : Timer 1 output Not used (returns "0" when read) (Do not write "1" to this bit.)
b7 b0
Timer 34 mode register (T34M: address 002916) Timer 3 count stop bit 0 : Count operation 1 : Count stop Timer 4 count stop bit 0 : Count operation 1 : Count stop Timer 3 count source selection bits 00 : f(XIN)/8 or f(XCIN)/16 01 : Underflow of Timer 2 10 : f(XIN)/16 or f(XCIN)/32 11 : f(XIN)/64 or f(XCIN)/128 Timer 4 count source selection bits 00 : f(XIN)/8 or f(XCIN)/16 01 : Underflow of Timer 3 10 : External count input CNTR1 (Note) 11 : Not available Timer 3 output selection bit (P46) 0 : I/O port 1 : Timer 3 output Not used (returns "0" when read) (Do not write "1" to this bit.)
b0
qTimer 5, Timer 6 The count sources of timer 5 and timer 6 can be selected by setting the timer 56 mode register. A rectangular waveform of timer 6 underflow signal divided by 2 can be output from the P44/PWM1 pin. qTimer 6 PWM1 Mode Timer 6 can output a PWM rectangular waveform with "H" duty cycle n/(n+m) from the P44/PWM1 pin by setting the timer 56 mode register (refer to Figure 18). The n is the value set in timer 6 latch (address 002516) and m is the value in the timer 6 PWM register (address 002716). If n is "0," the PWM output is "L," if m is "0," the PWM output is "H" (n = 0 is prior than m = 0). In the PWM mode, interrupts occur at the rising edge of the PWM output.
Timer 56 mode register (T56M: address 002A16) Timer 5 count stop bit 0 : Count operation 1 : Count stop Timer 6 count stop bit 0 : Count operation 1 : Count stop Timer 5 count source selection bit 0 : f(XIN)/8 or f(XCIN)/16 1 : Underflow of Timer 4 Timer 6 operation mode selection bit 0 : Timer mode 1 : PWM mode Timer 6 count source selection bits 00 : f(XIN)/8 or f(XCIN)/16 01 : Underflow of Timer 5 10 : Underflow of Timer 4 11 : Not available Timer 6 (PWM) output selection bit (P4 4) 0 : I/O port 1 : Timer 6 output Not used (returns "0" when read) (Do not write "1" to this bit.) Note: In the mask option type P, CNTR1 function cannot be used.
Fig. 16 Structure of timer related register
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HARDWARE
FUNCTIONAL DESCRIPTION
Data bus
XCIN 1/2 "1" XIN "0"
Internal system clock selection bit Timer 1 latch (8) RESET STP instruction Timer 1 interrupt request Timer 1 count source Timer 1 (8)
"01" selection bits "00" "10" "11"
FF16
1/8 1/16 1/64
Timer 1 count stop bit
P45/T1OUT
P45 latch
1/2
Timer 1 output selection bit Timer 2 latch (8) Timer 2 count source selection bits Timer 2 (8) P45 direction register
"00" "01" "10"
Rising/Falling active edge switch
0116 Timer 2 interrupt request
Timer 2 count stop bit
P61/CNTR0/CNTR2
Timer 3 latch (8) Timer 3 count source selection bits Timer 3 (8) Timer 3 count stop bit Timer 3 interrupt request
"01" "00" P46/T3OUT
P46 latch
"10" "11"
1/2
Timer 3 output selection bit Timer 4 latch (8)
"01"
P46 direction register
Timer 4 count source selection bits Timer 4 (8) Timer 4 count stop bit Timer 4 interrupt request
"00" "10"
P60/CNTR1 (Note)
Rising/Falling active edge switch
Timer 5 latch (8)
"1" "0"
Timer 5 count source selection bit Timer 5 (8) Timer 5 count stop bit Timer 5 interrupt request
Timer 6 latch (8)
"01" "00" "10"
Timer 6 count source selection bits Timer 6 (8) Timer 6 count stop bit Timer 6 interrupt request
Timer 6 PWM register (8)
P44/PWM1
P44 latch
"1" "0"
Timer 6 output selection bit
PWM
1/2
Timer 6 operation mode selection bit
P44 direction register
Note: In the mask option type P, CNTR1 function cannot be used.
Fig. 17 Block diagram of timer
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FUNCTIONAL DESCRIPTION
ts Timer 6 count source
Timer 6 PWM mode n ! ts m ! ts (n+m) ! ts
Timer 6 interrupt request
Timer 6 interrupt request
Note: PWM waveform (duty : n/(n + m) and period: (n + m) ! ts) is output. n : setting value of Timer 6 m: setting value of Timer 6 PWM register ts: period of Timer 6 count source
Fig. 18 Timing chart of timer 6 PWM1 mode
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FUNCTIONAL DESCRIPTION
16-Bit Timer
Timer X is a 16-bit timer that can be selected in one of four modes by the Timer X mode registers 1, 2 and can be controlled the timer X write and the real time port by setting the timer X mode registers. Read and write operation on 16-bit timer must be performed for both high- and low-order bytes. When reading a 16-bit timer, read from the high-order byte first. When writing to 16-bit timer, write to the loworder byte first. The 16-bit timer cannot perform the correct operation when reading during write operation, or when writing during read operation. qTimer X Timer X is a down-counter. When the timer reaches "000016," an underflow occurs with the next count pulse. Then the contents of the timer latch is reloaded into the timer and the timer continues downcounting. When a timer underflows, the interrupt request bit corresponding to that timer is set to "1." (1) Timer mode A count source can be selected by setting the Timer X count source selection bits (bits 1 and 2) of the Timer X mode register 1. (2) Pulse output mode Each time the timer underflows, a signal output from the CNTR2 pin is inverted. Except for this, the operation in pulse output mode is the same as in timer mode. When using a timer in this mode, set the port shared with the CNTR2 pin to output. (3) Event counter mode The timer counts signals input through the CNTR2 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the port shared with the CNTR2 pin to input. (4) Pulse width measurement mode A count source can be selected by setting the Timer X count source selection bits (bits 1 and 2) of the Timer X mode register 1. When CNTR2 active edge switch bit is "0," the timer counts while the input signal of the CNTR2 pin is at "H." When it is "1," the timer counts while the input signal of the CNTR2 pin is at "L." When using a timer in this mode, set the port shared with the CNTR2 pin to input.
s Note
*Timer X Write Control If the timer X write control bit is "0," when the value is written in the address of timer X, the value is loaded in the timer X and the latch at the same time. If the timer X write control bit is "1," when the value is written in the address of timer X, the value is loaded only in the latch. The value in the latch is loaded in timer X after timer X underflows. When the value is written in latch only, unexpected value may be set in the high-order counter if the writing in high-order latch and the underflow of timer X are performed at the same timing. *Real Time Port Control While the real time port function is valid, data for the real time port are output from ports P85 and P86 each time the timer X underflows. (However, if the real time port control bit is changed from "0" to "1," data are output without the timer X.) When the data for the real time port is changed while the real time port function is valid, the changed data are output at the next underflow of timer X. Before using this function, set the corresponding port direction registers to output mode.
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FUNCTIONAL DESCRIPTION
Real time port control bit "1" P85
Data bus QD P85 data for real time port Real time port control bit (P85) "0" "1" Timer X mode register write signal
"0" Latch P85 direction register P85 latch Real time port control bit "1" QD P86 "0" Latch P86 direction register P86 latch
P86 data for real time port Real time port control bit (P86) "0" "1"
XCIN
1/2 @"1"
Timer X mode register write signal
Internal system clock selection bit 1/2 XIN Count source selection bit 1/8 "0" 1/64 Timer X stop Timer X write control bit control bit Timer X operating mode bits CNTR2 active Timer X latch (low-order) (8) Timer X latch (high-order) (8) edge switch bit "00","01","11" "0" P61/CNTR0/CNTR2 Timer X (low-order) (8) Timer X (high-order) (8) "10" "1" Pulse width measurement mode Pulse output mode CNTR2 active edge switch bit "0" S Q T "1" Q P61 direction register P61 latch Divider Pulse output mode CNTR0
Timer X interrupt request
Fig. 19 Block diagram of timer X
b7
b0
b7
b0
Timer X mode register 1 (TXM1 : address 002E16) Timer X write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Timer X count source selection bits b2 b1 0 0 : f(XIN)/2 or f(XCIN)/4 0 1 : f(XIN)/8 or f(XCIN)/16 1 0 : f(XIN)/64 or f(XCIN)/128 1 1 : Not available Not used (returns "0" when read) Timer X operating mode bits b5 b4 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR2 active edge switch bit 0 : * Event counter mode ; counts rising edges * Pulse output mode ; output starts with "H" level * Pulse width measurement mode ; measures "H" periods 1 : * Event counter mode ; counts falling edges * Pulse output mode ; output starts with "L" level * Pulse width measurement mode ; measures "L" periods Timer X stop control bit 0 : Count operating 1 : Count stop
Timer X mode register 2 (TXM2 : address 002F16) Real time port control bit (P85) 0 : Real time port function is invalid 1 : Real time port function is valid Real time port control bit (P86) 0 : Real time port function is invalid 1 : Real time port function is valid P85 data for real time port P86 data for real time port Not used (returns "0" when read)
Fig. 20 Structure of timer X related registers
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FUNCTIONAL DESCRIPTION
Serial I/O qSerial I/O1
Serial I/O1 is used as the clock synchronous serial I/O and has an ordinary mode and an automatic transfer mode. In the automatic transfer mode, serial transfer is performed through the serial I/O automatic transfer RAM which has up to 256 bytes (addresses 0F0016 to 0FFF16: addresses 0F6016 to 0FFF16 are also used as FLD automatic display RAM). The P62/SRDY1/AN8, P64/INT4/SBUSY1/AN10, and P65/SSTB1/AN11 pins each have a handshake I/O signal function and can select either "H" active or "L" active for active logic.
Main address bus
Local address bus
Serial I/O automatic transfer RAM (0F0016--0FFF16)
Main Local data bus data bus
Address decoder
Serial I/O1 automatic transfer data pointer Serial I/O1 automatic transfer controller
XCIN
1/2
Internal system clock selection bit "1" "0"
Serial I/O1 control register 3
1/4 1/8 1/16 1/32 1/64 1/128 1/256
XIN
"0"
(P65/SSTB1 pin control bit)
P65/SSTB1
P62/SRDY1*P64/SBUSY1 pin control bit
"1"
P64 latch
"0" Serial I/O1 synchronous clock selection bit "0" Synchronous circuit SCLK1
P64/SBUSY1
"1" P62/SRDY1*P64/SBUSY1 P62 latch pin control bit "0"
P62/SRDY1
"1"
"1"
Serial I/O1 clock pin selection bit
"0"
"1"
Divider
P65 latch
Internal synchronous clock selection bits
Serial transfer status flag P52 latch
"0"
Serial I/O1 interrupt request
P52/SCLK11
"1" "1"
"0"
Serial I/O1 counter
"1"
Serial I/O1 clock pin selection bits
P53/SCLK12
"0"
P53 latch
"0"
P51/SOUT1
P51 latch
"1" Serial transfer selection bits
P50/SIN1
Serial I/O1 register (8)
Fig. 21 Block diagram of serial I/O1
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FUNCTIONAL DESCRIPTION
b7
b0 Serial I/O1 control register 1 (SIO1CON1 (SC11):address 001916) Serial transfer selection bits 00: Serial I/O disabled (pins P62,P64,P65,and P50--P53 are I/O ports) 01: 8-bit serial I/O 10: Not available 11: Automatic transfer serial I/O (8-bits) Serial I/O1 synchronous clock selection bits (P6 5/SSTB1 pin control bit) 00: Internal synchronous clock (P6 5 pin is an I/O port.) 01: External synchronous clock (P65 pin is an I/O port.) 10: Internal synchronous clock (P6 5 pin is an SSTB1 output.) 11: Internal synchronous clock (P6 5 pin is an SSTB1 output.) Serial I/O initialization bit 0: Serial I/O initialization 1: Serial I/O enabled Transfer mode selection bit 0: Full duplex (transmit and receive) mode (P5 0 pin is an SIN1 input.) 1: Transmit-only mode (P50 pin is an I/O port.) Transfer direction selection bit 0: LSB first 1: MSB first Serial I/O1 clock pin selection bit 0:SCLK11 (P53/SCLK12 pin is an I/O port.) 1:SCLK12 (P52/SCLK11 pin is an I/O port.)
b7
b0 Serial I/O1 control register 2 (SIO1CON2 (SC12): address 001A16) P62/SRDY1 * P64/SBUSY1 pin control bits 0000: Pins P62 and P64 are I/O ports 0001: Not used 0010: P62 pin is an SRDY1 output, P64 pin is an I/O port. 0011: P62 pin is an SRDY1 output, P64 pin is an I/O port. 0100: P62 pin is an I/O port, P64 pin is an SBUSY1 input. 0101: P62 pin is an I/O port, P64 pin is an SBUSY1 input. 0110: P62 pin is an I/O port, P64 pin is an SBUSY1 output. 0111: P62 pin is an I/O port, P64 pin is an SBUSY1 output. 1000: P62 pin is an SRDY1 input, P64 pin is an SBUSY1 output. 1001: P62 pin is an SRDY1 input, P64 pin is an SBUSY1 output. 1010: P62 pin is an SRDY1 input, P64 pin is an SBUSY1 output. 1011: P62 pin is an SRDY1 input, P64 pin is an SBUSY1 output. 1100: P62 pin is an SRDY1 output, P64 pin is an SBUSY1 input. 1101: P62 pin is an SRDY1 output, P64 pin is an SBUSY1 input. 1110: P62 pin is an SRDY1 output, P64 pin is an SBUSY1 input. 1111: P62 pin is an SRDY1 output, P64 pin is an SBUSY1 input. SBUSY1 output * SSTB1 output function selection bit (Valid in automatic transfer mode) 0: Functions as each 1-byte signal 1: Functions as signal for all transfer data Serial transfer status flag 0: Serial transfer completion 1: Serial transferring SOUT1 pin control bit (at no-transfer serial data) 0: Output active 1: Output high-impedance P51/SOUT1 P-channel output disable bit 0: CMOS 3-state (P-channel output is valid.) 1: N-channel open-drain (P-channel output is invalid.)
Fig. 22 Structure of serial I/O1 control registers 1, 2
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FUNCTIONAL DESCRIPTION
(1) Serial I/O1 Operation Either the internal synchronous clock or external synchronous clock can be selected by the serial I/O1 synchronous clock selection bits (b2 and b3 of address 001916) of serial I/O1 control register 1 as synchronous clock for serial transfer. The internal synchronous clock has a built-in dedicated divider where 7 different clocks are selected by the internal synchronous clock selection bits (b5, b6 and b7 of address 001C16) of serial I/O1 control register 3. The P62/SRDY1/AN8, P64/INT4/SBUSY1/AN10, and P65/SSTB1/AN11 pins each select either I/O port or handshake I/O signal by the serial I/O1 synchronous clock selection bits (b2 and b3 of address 001916) of serial I/O1 control register 1 as well as the P62/SRDY1 * P64/SBUSY1 pin control bits (b0 to b3 of address 001A16) of serial I/O1 control register 2. For the SOUT1 being used as an output pin, either CMOS output or N-channel open-drain output is selected by the P51/SOUT1 P-channel output disable bit (b7 of address 001A16) of serial I/O1 control register 2. Either output active or high-impedance can be selected as a SOUT1 pin state at serial non-transfer by the SOUT1 pin control bit (b6 of address 001A16) of serial I/O1 control register 2. However, when the external synchronous clock is selected, perform the following setup to put the SOUT1 pin into a high-impedance state. When the SCLK1 input is "H" after completion of transfer, set the SOUT1 pin control bit to "1." When the SCLK1 input goes to "L" after the start of the next serial transfer, the SOUT1 pin control bit is automatically reset to "0" and put into an output active state. Regardless of whether the internal synchronous clock or external synchronous clock is selected, the full duplex mode and the transmit-only mode are available for serial transfer, one of which is selected by the transfer mode selection bit (b5 of address 001916) of serial I/O1 control register 1. Either LSB first or MSB first is selected for the I/O sequence of the serial transfer bit strings by the transfer direction selection bit (b6 of address 001916) of serial I/O1 control register 1. When using serial I/O1, first select either 8-bit serial I/O or automatic transfer serial I/O by the serial transfer selection bits (b0 and b1 of address 001916) of serial I/O1 control register 1, after completion of the above bit setup. Next, set the serial I/O initialization bit (b4 of address 001916) of serial I/O1 control register 1 to "1" (Serial I/O enable) . When stopping serial transfer while data is being transferred, regardless of whether the internal or external synchronous clock is selected, reset the serial I/O initialization bit (b4) to "0."
b7
b0 Serial I/O1 control register 3 (SIO1CON3 (SC13): address 001C16) Automatic transfer interval set bits 00000: 2 cycles of transfer clocks 00001: 3 cycles of transfer clocks : 11110: 32 cycles of transfer clocks 11111: 33 cycles of transfer clocks Data is written to a latch and read from a decrement counter. Internal synchronous clock selection bits 000: f(XIN)/4 or f(XCIN)/8 001: f(XIN)/8 or f(XCIN)/16 010: f(XIN)/16 or f(XCIN)/32 011: f(XIN)/32 or f(XCIN)/64 100: f(XIN)/64 or f(XCIN)/128 101: f(XIN)/128 or f(XCIN)/256 110: f(XIN)/256 or f(XCIN)/512
Fig. 23 Structure of serial I/O1 control register 3
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(2) 8-bit Serial I/O Mode Address 001B16 is assigned to the serial I/O1 register. When the internal synchronous clock is selected, a serial transfer of the 8-bit serial I/O is started by a write signal to the serial I/O1 register (address 001B16). The serial transfer status flag (b5 of address 001A16) of serial I/O1 control register 2 indicates the shift register status of serial I/O1, and is set to "1" by writing into the serial I/O1 register, which becomes a transfer start trigger and reset to "0" after completion of 8bit transfer. At the same time, a serial I/O1 interrupt request occurs. When the external synchronous clock is selected, the contents of the serial I/O1 register are continuously shifted while transfer clocks are input to SCLK1. Therefore, the clock needs to be controlled externally. (3) Automatic Transfer Serial I/O Mode The serial I/O1 automatic transfer controller controls the write and read operations of the serial I/O1 register, so the function of address 001B16 is used as a transfer counter (1-byte units). When performing serial transfer through the serial I/O automatic transfer RAM (addresses 0F0016 to 0FFF16), it is necessary to set the serial I/O1 automatic transfer data pointer (address 001816) beforehand. Input the low-order 8 bits of the first data store address to be serially transferred to the automatic transfer data pointer set bits. When the internal synchronous clock is selected, the transfer interval for each 1-byte data can be set by the automatic transfer interval set bits (b0 to b4 of address 001C16) of serial I/O1 control register 3 in the following cases: 1. When using no handshake signal 2. When using the SRDY1 output, SBUSY1 output, and SSTB1 output of the handshake signal independently 3. When using a combination of SRDY1 output and SSTB1 output or a combination of SBUSY1 output and SSTB1 output of the handshake signal It is possible to select one of 32 different values, namely 2 to 33 cycles of the transfer clock, as a setting value. When using the SBUSY1 output and selecting the SBUSY1 output * SSTB1 output function selection bit (b4 of address 001A16) of serial I/O1 control register 2 as the signal for all transfer data, provided that the automatic transfer interval setting is valid, a transfer interval is placed before the start of transmission/reception of the first data and after the end of transmission/reception of the last data. For SSTB1 output, regardless of the contents of the SBUSY1 output * SSTB1 output function selection bit (b4), the transfer interval for each 1-byte data is longer than the set value by 2 cycles. Furthermore, when using a combination of SBUSY1 output and SSTB1 output as a signal for all transfer data, the transfer interval after the end of transmission/reception of the last data is longer than the set value by 2 cycles. When the external synchronous clock is selected, automatic transfer interval setting is disabled. After completion of the above bit setup, if the internal synchronous clock is selected, automatic serial transfer is started by writing the value of "number of transfer bytes - 1" into the transfer counter (address 001B16). When the external synchronous clock is selected, write the value of "number of transfer bytes - 1" into the transfer counter and input an internal system clock interval of 5 cycles or more. After that, input transfer clock to SCLK1. As a transfer interval for each 1-byte data transfer, input an internal system clock interval of 5 cycles or more from the clock rise time of the last bit. Regardless of whether the internal or external synchronous clock is selected, the automatic transfer data pointer and the transfer counter are decremented after each 1-byte data is received and then written into the automatic transfer RAM. The serial transfer status flag (b5 of address 001A16) is set to "1" by writing data into the transfer counter. Writing data becomes a transfer start trigger, and the serial transfer status flag is reset to "0" after the last data is written into the automatic transfer RAM. At the same time, a serial I/O1 interrupt request occurs. The values written in the automatic transfer data pointer set bits (b0 to b7 of address 001816) and the automatic transfer interval set bits (b0 to b4 of address 001C16) are held in the latch. When data is written into the transfer counter, the values latched in the automatic transfer data pointer set bits (b0 to b7) and the automatic transfer interval set bits (b0 to b4) are transferred to the decrement counter.
b7
b0 Serial I/O1 automatic transfer data pointer (SIO1DP: address 001816) Automatic transfer data pointer set bits Specify the low-order 8 bits of the first data store address on the serial I/O automatic transfer RAM. Data is written into the latch and read from the decrement counter.
Fig. 24 Structure of serial I/O1 automatic transfer data pointer
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FUNCTIONAL DESCRIPTION
Automatic transfer RAM FFF16
Automatic transfer data pointer
5216
F5216 F5116 F5016 F4F16 F4E16
Transfer counter
0416
F0016
SIN1
Serial I/O1 register
SOUT1
Fig. 25 Automatic transfer serial I/O operation
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HARDWARE
FUNCTIONAL DESCRIPTION
(4) Handshake Signal 1. SSTB1 output signal The SSTB1 output is a signal to inform an end of transmission/reception to the serial transfer destination . The SSTB1 output signal can be used only when the internal synchronous clock is selected. In the initial status, namely, in the status in which the serial I/O initialization bit (b4) is reset to "0," the SSTB1 output goes to "L," or the SSTB1 output goes to "H." At the end of transmit/receive operation, when the data of the serial I/O1 register is all output from SOUT1, pulses are output in the period of 1 cycle of the transfer clock so as to cause the SSTB1 output to go "H" or the SSTB1 output to go "L." After that, each pulse is returned to the initial status in which SSTB1 output goes to "L" or the SSTB1 output goes to "H." Furthermore, after 1 cycle, the serial transfer status flag (b5) is reset to "0." In the automatic transfer serial I/O mode, whether the SSTB1 output is to be active at an end of each 1-byte data or after completion of transfer of all data can be selected by the SBUSY1 output * SSTB1 output function selection bit (b4 of address 001A16) of serial I/O1 control register 2.
SBUSY1
SCLK1
SOUT1
Fig. 27 SBUSY1 input operation (internal synchronous clock) When the external synchronous clock is selected, input an "H" level signal into the SBUSY1 input and an "L" level signal into the SBUSY1 input in the initial status in which transfer is stopped. At this time, the transfer clocks to be input in SCLK1 become invalid. During serial transfer, the transfer clocks to be input in SCLK1 become valid, enabling a transmit/receive operation, while an "L" level signal is input into the SBUSY1 input and an "H" level signal is input into the SBUSY1 input. When changing the input values in the SBUSY1 input and the SBUSY1 input at these operations, change them when the SCLK1 input is in a high state. When the high impedance of the SOUT1 output is selected by the SOUT1 pin control bit (b6), the SOUT1 output becomes active, enabling serial transfer by inputting a transfer clock to SCLK1, while an "L" level signal is input into the SBUSY1 input and an "H" level signal is input into the SBUSY1 input.
SSTB1
Serial transfer status flag
SCLK1
SOUT1
Fig. 26 SSTB1 output operation 2. SBUSY1 input signal The SBUSY1 input is a signal which receives a request for a stop of transmission/reception from the serial transfer destination. When the internal synchronous clock is selected, input an "H" level signal into the SBUSY1 input and an "L" level signal into the SBUSY1 input in the initial status in which transfer is stopped. When starting a transmit/receive operation, input an "L" level signal into the SBUSY1 input and an "H" level signal into the SBUSY1 input in the period of 1.5 cycles or more of the transfer clock. Then, transfer clocks are output from the SCLK1 output. When an "H" level signal is input into the SBUSY1 input and an "L" level signal into the SBUSY1 input after a transmit/receive operation is started, this transmit/receive operation are not stopped immediately and the transfer clocks from the SCLK1 output is not stopped until the specified number of bits are transmitted and received. The handshake unit of the 8-bit serial I/O is 8 bits and that of the automatic transfer serial I/O is 8 bits.
SBUSY1
SCLK1 Invalid SOUT1
(Output high-impedance)
Fig. 28 SBUSY1 input operation (external synchronous clock) 3. SBUSY1 output signal The SBUSY1 output is a signal which requests a stop of transmission/reception to the serial transfer destination. In the automatic transfer serial I/O mode, regardless of the internal or external synchronous clock, whether the SBUSY1 output is to be active at transfer of each 1-byte data or during transfer of all data can be selected by the SBUSY1 output * SSTB1 output function selection bit (b4). In the initial status, the status in which the serial I/O initialization bit (b4) is reset to "0," the SBUSY1 output goes to "H" and the SBUSY1 output goes to "L."
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HARDWARE
FUNCTIONAL DESCRIPTION
When the internal synchronous clock is selected, in the 8-bit serial I/O mode and the automatic transfer serial I/O mode (SBUSY1 output function outputs in 1-byte units), the SBUSY1 output goes to "L" and the SBUSY1 output goes to "H" before 0.5 cycle (transfer clock) of the timing at which the transfer clock from the SCLK1 output goes to "L" at a start of transmit/receive operation. In the automatic transfer serial I/O mode (the SBUSY1 output function outputs all transfer data), the SBUSY1 output goes to "L" and the SBUSY1 output goes to "H" when the first transmit data is written into the serial I/O1 register (address 001B16). When the external synchronous clock is selected, the SBUSY1 output goes to "L" and the SBUSY1 output goes to "H" when transmit data is written into the serial I/O1 register to start a transmit operation, regardless of the serial I/O transfer mode. At termination of transmit/receive operation, the SBUSY1 output returns to "H" and the SBUSY1 output returns to "L", the initial status, when the serial transfer status flag is set to "0", regardless of whether the internal or external synchronous clock is selected. Furthermore, in the automatic transfer serial I/O mode (SBUSY1 output function outputs in 1-byte units), the SBUSY1 output goes to "H" and the SBUSY1 output goes to "L" each time 1-byte of receive data is written into the automatic transfer RAM.
SBUSY1
Serial transfer status flag
SBUSY1
Serial transfer status flag
SCLK1
SCLK1
Write to Serial I/O1 register
SOUT1
Fig. 29 SBUSY1 output operation (internal synchronous clock, 8-bits serial I/O)
Fig. 30 SBUSY1 output operation (external synchronous clock, 8-bits serial I/O)
Automatic transfer interval SCLK1
Serial I/O1 register Automatic transfer RAM Automatic transfer RAM Serial I/O1 register
SBUSY1
Serial transfer status flag
SOUT1
Fig. 31 SBUSY1 output operation in automatic transfer serial I/O mode (internal synchronous clock, SBUSY1 output function outputs each 1-byte)
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FUNCTIONAL DESCRIPTION
4. SRDY1 output signal The SRDY1 output is a transmit/receive enable signal which informs the serial transfer destination that transmit/receive is ready. In the initial status, when the serial I/O initialization bit (b4) is reset to "0," the SRDY1 output goes to "L" and the SRDY1 output goes to "H". After transmitted data is stored in the serial I/O1 register (address 001B16) and a transmit/receive operation becomes ready, the SRDY1 output goes to "H" and the SRDY1 output goes to "L". When a transmit/ receive operation is started and the transfer clock goes to "L", the SRDY1 output goes to "L" and the SRDY1 output goes to "H". 5. SRDY1 input signal The SRDY1 input signal becomes valid only when the SRDY1 input and the SBUSY1 output are used. The SRDY1 input is a signal for receiving a transmit/receive ready completion signal from the serial transfer destination. When the internal synchronous clock is selected, input a low level signal into the SRDY1 input and a high level signal into the SRDY1 input in the initial status in which the transfer is stopped. When an "H" level signal is input into the SRDY1 input and an "L" level signal is input into the SRDY1 input for a period of 1.5 cycles or more of transfer clock, transfer clocks are output from the SCLK1 output and a transmit/receive operation is started. After the transmit/receive operation is started and an "L" level signal is input into the SRDY1 input and an "H" level signal into the SRDY1 input, this operation cannot be immediately stopped. After the specified number of bits are transmitted and received, the transfer clocks from the SCLK1 output is stopped. The handshake unit of the 8-bit serial I/O and that of the automatic transfer serial I/O are of 8 bits. When the external synchronous clock is selected, the SRDY1 input becomes one of the triggers to output the SBUSY1 signal. To start a transmit/receive operation (SBUSY1 output: "L," SBUSY1 output: "H"), input an "H" level signal into the SRDY1 input and an "L" level signal into the SRDY1 input, and also write transmit data into the serial I/O1 register.
SRDY1
SCLK1
Write to serial I/O1 register
Fig. 32 SRDY1 output operation
SRDY1
SCLK1
SOUT1
Fig. 33 SRDY1 input operation (internal synchronous clock)
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FUNCTIONAL DESCRIPTION
A:
SCLK1 SRDY1 SBUSY1 SCLK1 SRDY1 SBUSY1
Write to serial I/O1 register
SRDY1
SBUSY1
A:
Internal synchronous clock selection
B:
External synchronous clock selection
SCLK1
B:
Write to serial I/O1 register
Fig. 34 Handshake operation at serial I/O1 mutual connecting (1)
SCLK1 SRDY1 SBUSY1
SCLK1 SRDY1 SBUSY1
A:
Write to serial I/O1 register
SRDY1
SBUSY1
A:
Internal synchronous clock selection
B:
External synchronous clock selection
SCLK1
B:
Write to serial I/O1 register
Fig. 35 Handshake operation at serial I/O1 mutual connecting (2)
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FUNCTIONAL DESCRIPTION
qSerial I/O2
Serial I/O2 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation during serial I/O2 operation. (1) Clock Synchronous Serial I/O Mode The clock synchronous serial I/O mode can be selected by setting the serial I/O2 mode selection bit (b6) of the serial I/O2 control register (address 001D16) to "1." For clock synchronous serial I/O, the transmitter and the receiver must use the same clock for serial I/O2 operation. If an internal clock is used, transmit/receive is started by a write signal to the serial I/O2 transmit/receive buffer register (TB/ RB) (address 001F16). When P57 (SCLK22) is selected as a clock I/O pin, SRDY2 output function is invalid, and P56 (SCLK21) is used as an I/O port.
Data bus Address 001F16 Receive buffer register P54/RXD
"0"
Serial I/O2 control register
Address 001D16
Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit
Receive shift register Shift clock Serial I/O2 clock I/O pin selection bit
"1" "0"
P56/SCLK21 P57/SRDY2/SCLK22 XIN
Internal system clock selection bit Serial I/O2 synchronous clock selection bit
"0"
"1"
XCIN
1/2
"1"
BRG count source selection bit Division ratio 1/(n+1) Baud rate generator BRG clock Address 001616 1/4 switch bit Falling edge detector Shift clock Transmit shift register Transmit buffer register Address 001F16 Data bus Clock control circuit
1/4
P57/SRDY2/SCLK22 Serial I/O2 clock I/O pin selection bit
F/F
P55/TXD
Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O2 status register Address 001E16
Fig. 36 Block diagram of clock synchronous serial I/O2
Transmit/Receive shift clock (1/2--1/2048 of internal clock or external clock) Serial I/O2 output TxD Serial I/O2 input RxD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
Receive enable signal SRDY2 Write-in signal to serial I/O2 transmit/receive buffer register (address 001F16) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection
TBE = 1 TSC = 0
Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting transmit interrupt source selection bit (TIC) of the serial I/O2 control register. 2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1."
Fig. 37 Operation of clock synchronous serial I/O2 function
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FUNCTIONAL DESCRIPTION
(2) Asynchronous Serial I/O (UART) Mode The asynchronous serial I/O (UART) mode can be selected by clearing the serial I/O2 mode selection bit (b6) of the serial I/O2 control register (address 001D16) to "0." Eight serial data transfer formats can be selected and the transfer formats used by the transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer (the two buffers have the same address in memory). Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted, and the receive buffer can receive 2-byte data continuously.
Data bus Address 001F16 OE P54/RXD Receive buffer register Serial I/O2 control register Address 001D16 Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16 PE FE P56/SCLK21 P57/SRDY2/SCLK22 XIN
"1" "0" SP detector
Character length selection bit 7 bit ST detector Receive shift register 8 bit
Serial I/O2 clock I/O pin selection bit
Clock control circuit Serial I/O2 synchronous clock selection bit
UART control register Address 001716
"1"
Internal system clock selection bit
"0"
BRG count source selection bit
XCIN
1/2
"1"
BRG clock switch bit
1/4
Division ratio 1/(n+1) Baud rate generator Address 001616 Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Address 001E16
ST/SP/PA generator
1/16 P55/TXD Character length selection bit Transmit buffer register Address 001F16 Data bus Transmit shift register
Serial I/O2 status register
Fig. 38 Block diagram of UART serial I/O2
Transmit or receive clock Write-in signal to transmit buffer register
TBE=0 TSC=0 TBE=1 TBE=0 TBE=1 D0 D1 SP ST D0 D1 TSC=1* SP
Serial I/O2 output TXD
ST
Read-out signal from receive buffer register
1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit
RBF=0 RBF=1
* Generated at 2nd bit in 2-stop bit mode
RBF=1 ST D0 D1
Serial I/O2 input RXD
ST
D0
D1
SP
SP
Fig. 39 Operation of UART serial I/O2 function
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FUNCTIONAL DESCRIPTION
[Serial I/O2 Control Register] SIO2CON (001D16)
The serial I/O2 control register contains eight control bits for serial I/O2 functions. ter clears error flags OE, PE, FE, and SE (b3 to b6, respectively). Writing "0" to the serial I/O2 enable bit (SIOE : b7 of the serial I/O2 control register) also clears all the status flags, including the error flags. All bits of the serial I/O2 status register are initialized to "0" at reset, but if the transmit enable bit (b4) of the serial I/O2 control register has been set to "1," the transmit shift register shift completion flag (b2) and the transmit buffer empty flag (b0) become "1."
[UART Control Register] UARTCON (001716)
This is a 7 bit register containing four control bits, which are valid when UART is selected, two control bits, which are valid when using serial I/O2, and one control bit, which is always valid. Data format of serial data receive/transfer and the output structure of the P55/TxD pin, etc. are set by this register.
[Serial I/O2 Transmit Buffer Register/Receive Buffer Register] TB/RB (001F16)
The transmit buffer and the receive buffer are located in the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is "0".
[Serial I/O2 Status Register] SIO2STS (001E16)
The read-only serial I/O2 status register consists of seven flags (b0 to b6) which indicate the operating status of the serial I/O2 function and various errors. Three of the flags (b4 to b6) are only valid in the UART mode. The receive buffer full flag (b1) is cleared to "0" when the receive buffer is read. The error detection is performed at the same time data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A writing to the serial I/O2 status regis-
[Baud Rate Generator] BRG (001616)
The baud rate generator determines the baud rate for serial transfer. With the 8-bit counter having a reload register, the baud rate generator divides the frequency of the count source by 1/(n+1), where n is the value written to the baud rate generator.
b7
b0
Serial I/O2 status register (SIO2STS : address 001E16) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift register shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read)
b7
b0
Serial I/O2 control register (SIO2CON : address 001D16) BRG count source selection bit (CSS) 0: f(XIN) or f(XCIN)/2 or f(XCIN) 1: f(XIN)/4 or f(XCIN)/8 or f(XCIN)/4 Serial I/O2 synchronous clock selection bit (SCS) 0: BRG/ 4 (when clock synchronous serial I/O is selected) BRG/16 (UART is selected) 1: External clock input (when clock synchronous serial I/O is selected) External clock input/16 (UART is selected) SRDY2 output enable bit (SRDY) 0: P57 pin operates as ordinary I/O pin 1: P57 pin operates as SRDY2 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O2 mode selection bit (SIOM) 0: Asynchronous serial I/O (UART) 1: Clock synchronous serial I/O Serial I/O2 enable bit (SIOE) 0: Serial I/O2 disabled (pins P54 to P57 operate as ordinary I/O pins) 1: Serial I/O2 enabled (pins P54 to P57 operate as serial I/O pins)
b7
b0
UART control register (UARTCON : address 001716) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P55/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) BRG clock switch bit 0: XIN or XCIN (depends on internal system clock) 1: XCIN Serial I/O2 clock I/O pin selection bit 0: SCLK21 (P57/SCLK22 pin is used as I/O port or SRDY2 output pin.) 1: SCLK22 (P56/SCLK21 pin is used as I/O port.) Not used (return "1" when read)
Fig. 40 Structure of serial I/O2 related register
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FUNCTIONAL DESCRIPTION
FLD Controller
The 38B5 group has fluorescent display (FLD) drive and control circuits. The FLD controller consists of the following components: *40 pins for FLD control pins *FLDC mode register *FLD data pointer *FLD data pointer reload register *Tdisp time set register *Toff1 time set register *Toff2 time set register *Port P0FLD/port switch register *Port P2FLD/port switch register *Port P8FLD/port switch register *Port P8 FLD output control register *FLD automatic display RAM (max. 160 bytes) A gradation display mode can be used for bright/dark display as a display function.
Main address bus
Main data bus
Local data bus FLD/P P20/FLD0 FLD/P P21/FLD1 FLD/P P22/FLD2 8 FLD/P P23/FLD3 FLD/P P24/FLD4 FLD/P P25/FLD5 FLD/P P26/FLD6 FLD/P P27/FLD7 000416 0EFA16 FLD/P FLD/P FLD/P FLD/P FLD/P FLD/P FLD/P FLD/P 0EF916 P00/FLD8 P01/FLD9 P02/FLD10 8 P03/FLD11 P04/FLD12 P05/FLD13 P06/FLD14 P07/FLD15 000016 P10/FLD16 P11/FLD17 P12/FLD18 8 P13/FLD19 P14/FLD20 P15/FLD21 P16/FLD22 P17/FLD23 000216
0F6016
FLD automatic display RAM
Local address bus
0FFF16
FLDC mode register (0EF416)
FLD data pointer reload register (0EF816)
P30/FLD24 P31/FLD25 P32/FLD26 8 P33/FLD27 P34/FLD28 P35/FLD29 P36/FLD30 P37/FLD31 000616 FLD/P P80/FLD32 FLD/P P81/FLD33 FLD/P P82/FLD34 FLD/P P83/FLD35 8 FLD/P P84/FLD36 FLD/P P85/FLD37 FLD/P P86/FLD38 FLD/P P87/FLD39 001016 0EFB16 FLD blanking interrupt FLD digit interrupt
Address decoder
FLD data pointer (0EF816)
Timing generator
Fig. 41 Block diagram for FLD control circuit
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FUNCTIONAL DESCRIPTION
[FLDC Mode Register] FLDM
The FLDC mode register is a 8-bit register respectively which is used to control the FLD automatic display and to set the blanking time Tscan for key-scan.
b7
b0
FLDC mode register (FLDM: address 0EF416) Automatic display control bit (P0, P1, P2, P3, P8) 0 : General-purpose mode 1 : Automatic display mode Display start bit 0 : Stop display 1 : Display (start to display by switching "0" to "1") Tscan control bits 00 : FLD digit interrupt (at rising edge of each digit) 01 : 1 ! Tdisp FLD blanking interrupt 10 : 2 ! Tdisp (at falling edge of the last digit) 11 : 3 ! Tdisp Timing number control bit 0 : 16 timing mode 1 : 32 timing mode Gradation display mode selection control bit 0 : Not selecting 1 : Selecting (Note) Tdisp counter count source selection bit 0 : f(XIN)/16 or f(XCIN)/32 1 : f(XIN)/64 or f(XCIN)/128 High-breakdown voltage port drivability selection bit 0 : Drivability strong 1 : Drivability weak
Notes 1: When a gradation display mode is selected, a number of timing is max. 16 timing. (Set the timing number control bit to "0.") 2: When changing bit 4 (timing number control bit) or bit 5 (gradation display mode selection control bit), set "0" to bit 1 (display start bit) to perform at display stop state.
Fig. 42 Structure of FLDC mode register
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FUNCTIONAL DESCRIPTION
FLD automatic display pins
When the automatic display control bits of the FLDC mode register (address 0EF416) are set to "1," the ports of P0, P1, P2, P3 and P8 are used as FLD automatic display pins. When using the FLD automatic display mode, set each port to the FLD pin or the general-purpose port using the respective switch register in accordance with the number of segments and the number of digits. Table 9 Pins in FLD automatic display mode Port Name P0, P2, P80-P83 P1, P3 P84-P87 Automatic Display Pins FLD0-FLD15 FLD32-FLD35 FLD16-FLD31 FLD36-FLD39 Setting Method The individual bits of the FLD/port switch register (addresses 0EF916-0EFB16) can be set each pin either FLD port ("1") or general-purpose port ("0"). None (FLD only) The individual bits of the FLD/port switch register (address 0EFB16) can be set each pin to either FLD port ("1") or general-purpose port ("0"). The output can be reversed by the port P8 FLD output control register (address 0EFC16). The port output format is the CMOS output format. When using the port as a display pin, a driver must be installed externally. This setting is performed by writing a value into the FLD/port switch register (addresses 0EF916 to 0EFB16) of each port. This setting can be performed in units of bit. When "0" is set, the port is set to the general-purpose port. When "1" is set, the port is set to the FLD pin. There is no restriction on whether the FLD pin is to be used as a segment pin or a digit pin.
Setting example 1 Number of segments Number of digits
Setting example 2
Setting example 3
Setting example 4
15 8
25 15
1 FLD0(SEG1) 1 FLD1(SEG2) 1 FLD2(SEG3) 1 FLD3(SEG4) 1 FLD4(SEG5) 1 FLD5(SEG6) 1 FLD6(SEG7) 1 FLD7(SEG8) 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 FLD8(SEG9) FLD9(SEG10) FLD10(SEG11) FLD11(SEG12) FLD12(SEG13) FLD13(SEG14) FLD14(SEG15) FLD15(SEG16) FLD16(DIG1) FLD17(DIG2) FLD18(DIG3) FLD19(DIG4) FLD20(DIG5) FLD21(DIG6) FLD22(DIG7) FLD23(DIG8) FLD24(DIG9) 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
18 20
P20 P21 FLD2(SEG1) FLD3(SEG2) FLD4(SEG3) FLD5(SEG4) FLD6(SEG5) FLD7(SEG6) FLD8(DIG1) FLD9(DIG2) FLD10(DIG3) FLD11(DIG4) FLD12(DIG5) FLD13(DIG6) FLD14(DIG7) FLD15(DIG8) FLD16(DIG9) FLD17(DIG10) FLD18(DIG11) FLD19(DIG12) FLD20(DIG13) FLD21(DIG14) FLD22(DIG15) FLD23(DIG16) FLD24(DIG17) FLD25(DIG18) FLD26(DIG19) FLD27(DIG20) FLD28(SEG7) FLD29(SEG8) FLD30(SEG9) 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
16 10
P20 P21 P22 P23 0 P24 0 P25 1 FLD4(SEG1) 1 FLD5(SEG2) 1 1 1 1 1 1 1 1 FLD6(SEG3) FLD7(SEG4) FLD8(SEG5) FLD9(SEG6) FLD10(SEG7) FLD11(SEG8) FLD12(SEG9) FLD13(SEG10) FLD16(DIG1) FLD17(DIG2) FLD18(DIG3) FLD19(DIG4) FLD20(DIG5) FLD21(DIG6) FLD22(DIG7) FLD23(DIG8) FLD24(DIG9) 1 1 1 1 1 1 1 1
Port P2
0 P20 0 P21 0 P22 0 P23 0 P24 0 P25 0 P26 0 P27
Port P0
1 FLD8(SEG1) 0 P01 0 P02 0 P03 0 P04 0 P05 1 FLD14(SEG2) 1 FLD15(SEG3)
Port P1
FLD16(DIG1) FLD17(DIG2) FLD18(DIG3) FLD19(DIG4) FLD20(SEG4) FLD21(SEG5) FLD22(SEG6) FLD23(SEG7)
Port P3
FLD24(SEG8)
0 FLD25(SEG9) 0 FLD26(SEG10) 0 FLD27(SEG11) 0 FLD28(DIG5) 1 FLD29(DIG6) 1 FLD30(DIG7) 1 FLD31(DIG8) 1 1 1 1 1 1 1 1 1
1 FLD25(DIG10) 1 FLD26(DIG11) 1 FLD27(DIG12) 1 FLD28(DIG13) 1 FLD29(DIG14) 1 FLD30(DIG15) 1 FLD31(SEG17) 0 1 1 1 1 1 1 1
1 FLD25(DIG10) 1 FLD14(SEG11) 1 FLD15(SEG12) 1 FLD26(SEG13) 0 FLD27(SEG14) 0 FLD28(SEG15) 0 FLD29(SEG16) 0 0 0 0 0 0 0 0 0 P80 P81 P82 P83 P84 P85 P86 P87 Value of FLDRAM write disable register If data is set to "1", data is protected. This setting does not decide the FLD port function (SEG/DIG).
0 FLD31(SEG10) 0
Port P8
1 FLD32(SEG12) 1 FLD33(SEG13) 1 FLD34(SEG14) 1 FLD35(SEG15) 0 P84 0 P85 0 P86 0 P87 Value of FLD/port switch register
FLD32(SEG18) FLD33(SEG19) FLD34(SEG20) FLD35(SEG21) FLD36(SEG22) FLD37(SEG23) FLD38(SEG24) FLD39(SEG25)
FLD32(SEG11) FLD33(SEG12) FLD34(SEG13) FLD35(SEG14) FLD36(SEG15) FLD37(SEG16) FLD38(SEG17)
1 FLD39(SEG18)
Fig. 43 Segment/Digit setting example
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FUNCTIONAL DESCRIPTION
FLD automatic display RAM
The FLD automatic display RAM uses the 160 bytes of addresses 0F6016 to 0FFF16. For FLD, the 3 modes of 16-timing ordinary mode, 16-timing*gradation display mode and 32-timing mode are available depending on the number of timings and the presence/absence of gradation display. The automatic display RAM in each mode is as follows: (1) 16-timing*Ordinary Mode The 80 bytes of addresses 0FB016 to 0FFF16 are used as a FLD display data store area. Because addresses 0F6016 to 0FAF16 are not used as the automatic display RAM, they can be the ordinary RAM or serial I/O automatic transfer RAM. (2) 16-timing*Gradation Display Mode The 160 bytes of addresses 0F6016 to 0FFF16 are used. The 80 bytes of addresses 0FB016 to 0FFF16 are used as an FLD display data store area, while the 80 bytes of addresses 0F6016 to 0FAF16 are used as a gradation display control data store area. (3) 32-timing Mode The 160 bytes of addresses 0F6016 to 0FFF16 are used as an FLD display data store area.
[FLD Data Pointer and FLD Data Pointer Reload Register]
FLDDP (0EF816)
Both the FLD data pointer and FLD data pointer reload register are 8-bit registers assigned at address 0EF816. When writing data to this address, the data is written to the FLD data pointer reload register; when reading data from this address, the value in the FLD data pointer is read.
16-timing*ordinary mode 0F6016
Not used
16-timing*gradation display mode 0F6016
Gradation display control data stored area
32-timing mode
0F6016
0FB016
1 to 16 timing display data stored area
0FB016
1 to 16 timing display data stored area
1 to 32 timing display data stored area
0FFF16
0FFF16
0FFF16
Fig. 44 FLD automatic display RAM assignment
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HARDWARE
FUNCTIONAL DESCRIPTION
Data setup
(1) 16-timing*Ordinary Mode The area of addresses 0FB016 to 0FFF16 are used as a FLD automatic display RAM. When data is stored in the FLD automatic display RAM, the last data of FLD port P2 is stored at address 0FB016, the last data of FLD port P0 is stored at address 0FC016, the last data of FLD port P1 is stored at address 0FD016, the last data of FLD port P3 is stored at address 0FE016, and the last data of FLD port P8 is stored at address 0FF016, to assign in sequence from the last data respectively. The first data of the FLD port P2, P0, P1, P3, and P8 is stored at an address which adds the value of (the timing number - 1) to the corresponding address 0FB016, 0FC016, 0FD016, 0FE016, and 0FF016. Set the FLD data pointer reload register to the value given by the timing number - 1. "1" is always written to bits 7, 6, and 5. Note that "0" is always read from bits 7, 6, and 5 when reading. "1" is always set to bit 4, but this bit become written value when reading. (2) 16-timing*Gradation Display Mode Display data setting is performed in the same way as that of the 16-timing*ordinary mode. Gradation display control data is arranged at an address resulting from subtracting 005016 from the display data store address of each timing and pin. Bright display is performed by setting "0," and dark display is performed by setting "1." Set the FLD data pointer reload register to the value given by the timing number - 1. "1" is always written to bits 7, 6, and 5. Note that "0" is always read from bits 7, 6, and 5 when reading. "1" is always set to bit 4, but this bit become written value when reading. (3) 32-timing Mode The area of addresses 0F6016 to 0FFF16 are used as a FLD automatic display RAM. When data is stored in the FLD automatic display RAM, the last data of FLD port P2 is stored at address 0F6016, the last data of FLD port P0 is stored at address 0F8016, the last data of FLD port P1 is stored at address 0FA016, the last data of FLD port P3 is stored at address 0FC016, and the last data of FLD port P8 is stored at address 0FE016, to assign in sequence from the last data respectively. The first data of the FLD port P2, P0, P1, P3, and P8 is stored at an address which adds the value of (the timing number - 1) to the corresponding address 0F6016, 0F8016, 0FA016, 0FC016, and 0FE016. Set the FLD data pointer reload register to the value given by the timing number -1. "1" is always written to bits 7, 6, and 5. Note that "0" is always read from bits 7, 6, and 5 when reading.
Number of FLD segments: 15 Number of timing: 8 (FLD data pointer reload register = 7)
Bit Address
7
6
5
4
3
2
1
0
0FB016 0FB116 0FB216 0FB316 0FB416 0FB516 0FB616 0FB716 0FB816 0FB916 0FBA16 0FBB16 0FBC16 0FBD16 0FBE16 0FBF16 0FC016 0FC116 0FC216 0FC316 0FC416 0FC516 0FC616 0FC716 0FC816 0FC916 0FCA16 0FCB16 0FCC16 0FCD16 0FCE16 0FCF16 0FD016 0FD116 0FD216 0FD316 0FD416 0FD516 0FD616 0FD716 0FD816 0FD916 0FDA16 0FDB16 0FDC16 0FDD16 0FDE16 0FDF16 0FE016 0FE116 0FE216 0FE316 0FE416 0FE516 0FE616 0FE716 0FE816 0FE916 0FEA16 0FEB16 0FEC16 0FED16 0FEE16 0FEF16 0FF016 0FF116 0FF216 0FF316 0FF416 0FF516 0FF616 0FF716 0FF816 0FF916 0FFA16 0FFB16 0FFC16 0FFD16 0FFE16 0FFF16 Note:
The last timing (The last data of FLDP2)
Timing for start (The first data of FLDP2) FLDP2 data area
The last timing (The last data of FLDP0)
Timing for start (The first data of FLDP0) FLDP0 data area
The last timing (The last data of FLDP1)
Timing for start (The first data of FLDP1) FLDP1 data area
The last timing (The last data of FLDP3)
Timing for start (The first data of FLDP3) FLDP3 data area
The last timing (The last data of FLDP8)
Timing for start (The first data of FLDP8) FLDP8 data area
shaded area is used for segment. shaded area is used for digit.
Fig. 45 Example of using FLD automatic display RAM in 16-timing*ordinary mode
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FUNCTIONAL DESCRIPTION
Number of FLD segments: 25 Number of timing: 15 (FLD data pointer reload register = 14)
Bit Address
7
6
5
4
3
2
1
0
Bit Address
7
6
5
4
3
2
1
0
0FB016 0FB116 0FB216 0FB316 0FB416 0FB516 0FB616 0FB716 0FB816 0FB916 0FBA16 0FBB16 0FBC16 0FBD16 0FBE16 0FBF16 0FC016 0FC116 0FC216 0FC316 0FC416 0FC516 0FC616 0FC716 0FC816 0FC916 0FCA16 0FCB16 0FCC16 0FCD16 0FCE16 0FCF16 0FD016 0FD116 0FD216 0FD316 0FD416 0FD516 0FD616 0FD716 0FD816 0FD916 0FDA16 0FDB16 0FDC16 0FDD16 0FDE16 0FDF16 0FE016 0FE116 0FE216 0FE316 0FE416 0FE516 0FE616 0FE716 0FE816 0FE916 0FEA16 0FEB16 0FEC16 0FED16 0FEE16 0FEF16 0FF016 0FF116 0FF216 0FF316 0FF416 0FF516 0FF616 0FF716 0FF816 0FF916 0FFA16 0FFB16 0FFC16 0FFD16 0FFE16 0FFF16 Note:
The last timing (The last data of FLDP2)
FLDP2 data area
Timing for start (The first data of FLDP2) The last timing (The last data of FLDP0)
FLDP0 data area
Timing for start (The first data of FLDP0) The last timing (The last data of FLDP1)
FLDP1 data area
Timing for start (The first data of FLDP1) The last timing (The last data of FLDP3)
FLDP3 data area
Timing for start (The first data of FLDP3) The last timing (The last data of FLDP8)
FLDP8 data area
Timing for start (The first data of FLDP8) shaded area is used for segment. shaded area is used for digit.
0F6016 0F6116 0F6216 0F6316 0F6416 0F6516 0F6616 0F6716 0F6816 0F6916 0F6A16 0F6B16 0F6C16 0F6D16 0F6E16 0F6F16 0F7016 0F7116 0F7216 0F7316 0F7416 0F7516 0F7616 0F7716 0F7816 0F7916 0F7A16 0F7B16 0F7C16 0F7D16 0F7E16 0F7F16 0F8016 0F8116 0F8216 0F8316 0F8416 0F8516 0F8616 0F8716 0F8816 0F8916 0F8A16 0F8B16 0F8C16 0F8D16 0F8E16 0F8F16 0F9016 0F9116 0F9216 0F9316 0F9416 0F9516 0F9616 0F9716 0F9816 0F9916 0F9A16 0F9B16 0F9C16 0F9D16 0F9E16 0F9F16 0FA016 0FA116 0FA216 0FA316 0FA416 0FA516 0FA616 0FA716 0FA816 0FA916 0FAA16 0FAB16 0FAC16 0FAD16 0FAE16 0FAF16 Note:
The last timing (The last data of FLDP2)
FLDP2 gradation display data area
Timing for start (The first data of FLDP2) The last timing (The last data of FLDP0)
FLDP0 gradation display data area
Timing for start (The first data of FLDP0) The last timing (The last data of FLDP1)
FLDP1 gradation display data area
Timing for start (The first data of FLDP1) The last timing (The last data of FLDP3)
FLDP3 gradation display data area
Timing for start (The first data of FLDP3) The last timing (The last data of FLDP8)
FLDP8 gradation display data area
Timing for start (The first data of FLDP8) shaded area is used for gradation display data.
Fig. 46 Example of using FLD automatic display RAM in 16-timing*gradation display mode
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HARDWARE
FUNCTIONAL DESCRIPTION
Number of FLD segments: 18 Number of timing: 20 (FLD data pointer reload register = 19)
Bit Address
7
6
5
4
3
2
1
0
Bit Address
7
6
5
4
3
2
1
0
0FB016 0FB116 0FB216 0FB316 0FB416 0FB516 0FB616 0FB716 0FB816 0FB916 0FBA16 0FBB16 0FBC16 0FBD16 0FBE16 0FBF16 0FC016 0FC116 0FC216 0FC316 0FC416 0FC516 0FC616 0FC716 0FC816 0FC916 0FCA16 0FCB16 0FCC16 0FCD16 0FCE16 0FCF16 0FD016 0FD116 0FD216 0FD316 0FD416 0FD516 0FD616 0FD716 0FD816 0FD916 0FDA16 0FDB16 0FDC16 0FDD16 0FDE16 0FDF16 0FE016 0FE116 0FE216 0FE316 0FE416 0FE516 0FE616 0FE716 0FE816 0FE916 0FEA16 0FEB16 0FEC16 0FED16 0FEE16 0FEF16 0FF016 0FF116 0FF216 0FF316 0FF416 0FF516 0FF616 0FF716 0FF816 0FF916 0FFA16 0FFB16 0FFC16 0FFD16 0FFE16 0FFF16 Note:
Timing for start (The first data of FLDP1)
The last timing (The last data of FLDP3)
FLDP3 data area
Timing for start (The first data of FLDP3)
The last timing (The last data of FLDP8)
FLDP8 data area
Timing for start (The first data of FLDP8)
0F6016 0F6116 0F6216 0F6316 0F6416 0F6516 0F6616 0F6716 0F6816 0F6916 0F6A16 0F6B16 0F6C16 0F6D16 0F6E16 0F6F16 0F7016 0F7116 0F7216 0F7316 0F7416 0F7516 0F7616 0F7716 0F7816 0F7916 0F7A16 0F7B16 0F7C16 0F7D16 0F7E16 0F7F16 0F8016 0F8116 0F8216 0F8316 0F8416 0F8516 0F8616 0F8716 0F8816 0F8916 0F8A16 0F8B16 0F8C16 0F8D16 0F8E16 0F8F16 0F9016 0F9116 0F9216 0F9316 0F9416 0F9516 0F9616 0F9716 0F9816 0F9916 0F9A16 0F9B16 0F9C16 0F9D16 0F9E16 0F9F16 0FA016 0FA116 0FA216 0FA316 0FA416 0FA516 0FA616 0FA716 0FA816 0FA916 0FAA16 0FAB16 0FAC16 0FAD16 0FAE16 0FAF16
The last timing (The last data of FLDP2)
FLDP2 data area
Timing for start (The first data of FLDP2)
The last timing (The last data of FLDP0)
FLDP0 data area
Timing for start (The first data of FLDP0)
The last timing (The last data of FLDP1)
FLDP1 data area
shaded area is used for segment. shaded area is used for digit.
Fig. 47 Example of using FLD automatic display RAM in 32-timing mode
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FUNCTIONAL DESCRIPTION
Digit data protect function
The FLD automatic display RAM is provided with a data protect function that disables the RAM area data to be rewritten as digit data. This function can disable data from being written in optional bits in the RAM area corresponding to P1 to P3. A programming load can be reduced by protecting an area that requires no change after data such as digit data is written. Write digit data beforehand; then set "1" in the corresponding bits. With this, the setting is completed. The data protect area becomes the maximum RAM area of P1 and P3. For example, when bit 0 of P1 is protected in the 16timing*ordinary mode, bits 0 of RAM addresses 0FD016 to 0FDF16 can be protected. Likewise, in the 16-timing*gradation display mode, bits 0 of addresses 0FD016 to 0FDF16 and 0F8016 to 0F8F16 can be protected. In the 32-timing mode, bits 0 of addresses 0FA016 to 0FBF16 can be protected.
b7
b0 P1FLDRAM write disable register (P1FLDRAM : address 0EF216) FLDRAM corresponding to P10 FLDRAM corresponding to P11 FLDRAM corresponding to P12 FLDRAM corresponding to P13 FLDRAM corresponding to P14 FLDRAM corresponding to P15 FLDRAM corresponding to P16 FLDRAM corresponding to P17 0: Operating normally 1: Write disabled
b7
b0 P3FLDRAM write disable register (P3FLDRAM : address 0EF316) FLDRAM corresponding to P30 FLDRAM corresponding to P31 FLDRAM corresponding to P32 FLDRAM corresponding to P33 FLDRAM corresponding to P34 FLDRAM corresponding to P35 FLDRAM corresponding to P36 FLDRAM corresponding to P37 0: Operating normally 1: Write disabled
Fig. 48 Structure of FLDRAM write disable register
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HARDWARE
FUNCTIONAL DESCRIPTION
Setting method when using the grid scan type FLD
When using the grid scan type FLD, set "1" in the RAM area corresponding to the digit ports that output "1" at each timing. Set "0" in the RAM area corresponding to the other digit ports.
Number of FLD segments: 16 Number of timing: 10 (FLD data pointer reload register = 9)
Bit Address
7
6
5
4
3
2
1
0
Number of timing: 10
The first second third.......................9th 10th
DIG10 (P31)
DIG9 (P30)
DIG8 (P17)
DIG2 (P11)
DIG1 (P10)
Segment output
Fig. 49 Example of digit timing using grid scan type
0FB016 0FB116 0FB216 0FB316 0FB416 0FB516 0FB616 0FB716 0FB816 0FB916 0FBA16 0FBB16 0FBC16 0FBD16 0FBE16 0FBF16 0FC016 0FC116 0FC216 0FC316 0FC416 0FC516 0FC616 0FC716 0FC816 0FC916 0FCA16 0FCB16 0FCC16 0FCD16 0FCE16 0FCF16 0FD016 0FD116 0FD216 0FD316 0FD416 0FD516 0FD616 0FD716 0FD816 0FD916 0FDA16 0FDB16 0FDC16 0FDD16 0FDE16 0FDF16 0FE016 0FE116 0FE216 0FE316 0FE416 0FE516 0FE616 0FE716 0FE816 0FE916 0FEA16 0FEB16 0FEC16 0FED16 0FEE16 0FEF16 0FF016 0FF116 0FF216 0FF316 0FF416 0FF516 0FF616 0FF716 0FF816 0FF916 0FFA16 0FFB16 0FFC16 0FFD16 0FFE16 0FFF16 Note:
The last timing (The last data of FLDP2)
FLDP2 data area Timing for start (The first data of FLDP2)
The last timing (The last data of FLDP0)
FLDP0 data area Timing for start (The first data of FLDP0)
0 0 0 0 0 0 0 1 0 0
0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 1 0 0 0 0
0 0 0 0 1 0 0 0 0 0
0 0 0 1 0 0 0 0 0 0
0 0 1 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0
The last timing (The last data of FLDP1)
FLDP1 data area Timing for start (The first data of FLDP1)
0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 1 0
The last timing (The last data of FLDP3)
FLDP3 data area Timing for start (The first data of FLDP3)
The last timing (The last data of FLDP8)
FLDP8 data area Timing for start (The first data of FLDP8)
shaded area is used for segment. shaded area is used for digit.
Fig. 50 Example of using FLD automatic display RAM using grid scan type
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FUNCTIONAL DESCRIPTION
Timing setting
Each timing is set by the FLDC mode register, Tdisp time set register, Toff1 time set register, and Toff2 time set register. *Tdisp time setting Set the Tdisp time by the Tdisp counter count source selection bit of the FLDC mode register and the Tdisp time set register. Supposing that the value of the Tdisp time set register is n, the Tdisp time is represented as Tdisp = (n+1) ! t (t: count source synchronization). When the Tdisp counter count source selection bit of the FLDC mode register is "0" and the value of the Tdisp time set register is 200 (C816), the Tdisp time is: Tdisp = (200+1) ! 4 (at XIN= 4 MHz) = 804 s. When reading the Tdisp time set register, the value in the counter is read out. *Toff1 time setting Set the Toff1 time by the Toff1 time set register. Supposing that the value of the Toff1 time set register is n1, the Toff1 time is represented as Toff1 = n1 ! t. When the Tdisp counter count source selection bit of the FLDC mode register is "0" and the value of the Toff1 time set register is 30 (1E16), Toff1 = 30 ! 4 (at XIN = 4 MHz) = 120 s. Set a value of 0316 or more to the Toff1 time set register (address 0EF616). *Toff2 time setting Set the Toff2 time by the Toff2 time set register. Supposing that the value of the Toff2 time set register is n2, the Toff2 time is represented as Toff2 = n2 ! t. When the Tdisp counter count source selection bit of the FLDC mode register is "0" and the value of the Toff2 time set register is 180 (B416), Toff2 = 180 ! 4 (at XIN = 4 MHz) = 720 s. This Toff2 time setting is valid only for FLD ports which are in the gradation display mode and whose gradation display control RAM value is "1." When setting "1" to bit 7 of the P8FLD output control register (address 0EFC16), set a value of 0316 or more to the Toff2 time set register (address 0EF716).
Key-scan
When a key-scan is performed with the segment during key-scan blanking period Tscan, take the following sequence: 1. Write "0" to bit 0 of the FLDC mode register (address 0EF416). 2. Set the port corresponding to the segment for key-scan to the output port. 3. Perform the key-scan. 4. After the key-scan is performed, write "1" to bit 0 of FLDC mode register (address 0EF416). s Note When performing a key-scan according to the above step 1 to 4, take the following points into consideration. 1. Do not set "0" in bit 1 of the FLDC mode register (address 0EF416). 2. Do not set "1" in the ports corresponding to digits.
FLD automatic display start
To perform FLD automatic display, set the following registers. *Port P0FLD/port switch register *Port P2FLD/port switch register *Port P8FLD/port switch register *FLDC mode register *Tdisp time set register *Toff1 time set register *Toff2 time set register *FLD data pointer FLD automatic display mode is selected by writing "1" to the bit 0 of the FLDC mode register (address 0EF416), and the automatic display is started by writing "1" to bit 1. During FLD automatic display, bit 1 of the FLDC mode register (address 0EF416) always keeps "1," and FLD automatic display can be interrupted by writing "0" to bit 1.
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HARDWARE
FUNCTIONAL DESCRIPTION
Repeat synchronous Tdisp Segment Digit output Tn Tn-1 Tn-2 T4 T3 T2 T1 Tscan
FLD digit interrupt request occurs at the rising edge of digit (each timing).
Segment setting by software FLD blanking interrupt request occurs at the falling edge of the last timing.
Segment Digit Toff1 Tdisp
Segment Digit Toff1 Toff2 Tdisp n: Number of timing
When a gradation display mode is selected
Pin under the condition that bit 5 of the FLDC mode register is "1," and the corresponding gradation display control data value is "1."
Fig. 51 FLDC timing
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FUNCTIONAL DESCRIPTION
P84 to P87 FLD output reverse function
P84 to P87 are provided with a function to reverse the polarity of the FLD output. This function is useful in adjusting the polarity when using an externally installed driver. The output polarity can be reversed by setting "1" to bit 0 of the port P8 FLD output control register.
Segment Digit At Toff2 control bit = "0" in gradation display mode (at gradation display control data= "1") At Toff2 control bit = "1" in gradation display mode (at gradation display control data= "1")
P84 to P87 FLDRAM write disable function
This function can disable writing data in the RAM area corresponding to P84 to P87. This function can be set by setting "1" to bit 1 of the port P8FLD output control register (address 0EFC16).
Toff1 Toff2 Tdisp
P84 to P87 Toff invalid function
P84 to P87 can output waveform in which Toff is invalid, when P84 to P87 is selected FLD ports (See Figure 52). The function is useful when using a 4 bits 16 bits decoder. The Toff can be invalid by setting "1" to bit 2 of the port P8FLD output control register (address 0EFC16).
Dimmer signal P84-P87 Toff invalid P84-P87 Toff invalid Delay
P84 to P87 output delay function
P84 to P87 can output waveform in which is delayed for 16 s, when selecting FLD port and selecting Toff invalid function (See Figure 52). When using a 4 bits 16 bits decoder, the function can be useful for prevention of leak radiation caused by phase discrepancy between segment output waveform and digit output waveform. This function can be set by setting "1" to bit 3 of the port P8FLD output control register (address 0EFC16).
16 s
Fig. 52 P84 to P87 FLD output waveform
Toff2 SET/RESET change function
The value of the Toff2 time set register is valid when gradation display mode is selected. The FLD ports output (set) the data of display RAM at the end of the Toff1 time and output "0" (reset) at the end of the Toff2 time, when bit 7 of the port P8FLD output control register is "0". The FLD ports output (set) the data of display RAM at the end of the Toff2 time and output "0" (reset) at the end of Tdisp time, when bit 7 of the port P8FLD output control register is "1".
Dimmer signal output function
P63 can output the dimmer signal. When using a 4 bits 16 bits decoder, the dimmer signal can be used as a control signal for a 4 bits 16 bits decoder. When using M35501FP, the dimmer signal can be used as the CLK signal. The dimmer signal can be output by setting "1" to bit 4 of the port P8FLD output control register (address 0EFC16).
b7
b0 Port P8FLD output control register (P8FLDCON: address 0EFC16) P84-P87 FLD output reverse bit 0: Output normally 1: Reverse output P84-P87 FLDRAM write disable bit 0: Operating normally 1: Write disabled P84-P87 Toff invalid bit 0: Operating normally 1: Toff invalid P84-P87 delay control bit (Note) 0: No delay 1: Delay P63/AN9 dimmer output control bit 0: Ordinary port 1: Dimmer output Not used ("0" at reading) Toff2 control bit 0: Gradation display data is reset at Toff2 (set at Toff1) 1: Gradation display data is set at Toff2 (reset at Tdisp) Note: Valid only when selecting FLD port and P8 4-P87 Toff invalid function
Fig. 53 Structure of port P8 FLD output control register
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HARDWARE
FUNCTIONAL DESCRIPTION
A-D Converter
The 38B5 group has a 10-bit A-D converter. The A-D converter performs successive approximation conversion. conversion interrupt request bit to "1." Note that the comparator is constructed linked to a capacitor, so set f(XIN) to at least 250 kHz during A-D conversion. Use a CPU system clock dividing the main clock XIN as the internal system clock.
[A-D Conversion Register] AD
One of these registers is a high-order register, and the other is a loworder register. The high-order 8 bits of a conversion result is stored in the A-D conversion register (high-order) (address 003416), and the low-order 2 bits of the same result are stored in bit 7 and bit 6 of the A-D conversion register (low-order) (address 003316). During A-D conversion, do not read these registers.
b7 b0 A-D control register (ADCON: address 003216) Analog input pin selection bits 0000: P70/AN0 0001: P71/AN1 0010: P72/AN2 0011: P73/AN3 0100: P74/AN4 0101: P75/AN5 0110: P76/AN6 0111: P77/AN7 1000: P62/SRDY1/AN8 1001: P63/AN9 1010: P64/INT4/SBUSY1/AN10 1011: P65/SSTB1/AN11 AD conversion completion bit 0: Conversion in progress 1: Conversion completed Not used (returns "0" when read)
[A-D Control Register] ADCON
This register controls A-D converter. Bits 3 to 0 are analog input pin selection bits. Bit 4 is an AD conversion completion bit and "0" during A-D conversion. This bit is set to "1" upon completion of A-D conversion. A-D conversion is started by setting "0" in this bit.
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between AVSS and VREF, and outputs the divided voltages.
[Channel Selector]
The channel selector selects one of the input ports P77/AN7-P70/ AN0, and P65/SSTB1/AN11-P62/SRDY1/AN8 and inputs it to the comparator. When port P64 is selected as an analog input pin, an external interrupt function (INT4) is invalid.
b7
b0 A-D conversion register (high-order) (ADH: address 003416) AD conversion result stored bits
b7
b0 A-D conversion register (low-order) (ADL: address 003316)
[Comparator and Control Circuit]
The comparator and control circuit compares an analog input voltage with the comparison voltage and stores the result in the A-D conversion register. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD
Not used (returns "0" when read) AD conversion result stored bits
Fig. 54 Structure of A-D control register
Data bus
b7 b0
A-D control register
4 P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 P62/SRDY1/AN8 P63/AN9 P64/INT4/SBUSY1/AN10 P65/SSTB1/AN11 A-D control circuit A-D interrupt request
Channel selector
Comparator
A-D conversion register (H) A-D conversion register (L) (Address 003416) (Address 003316)
Resistor ladder
AVSS @VREF
Fig. 55 Block diagram of A-D converter
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FUNCTIONAL DESCRIPTION
Pulse Width Modulation (PWM)
The 38B5 group has a PWM function with a 14-bit resolution. When the oscillation frequency XIN is 4 MHz, the minimum resolution bit width is 250 ns and the cycle period is 4096 s. The PWM timing generator supplies a PWM control signal based on a signal that is the frequency of the XIN clock. The explanation in the rest assumes XIN = 4 MHz.
Data bus
It is set to "1" when write.
PWM register (low-order) (address 001516)
bit7 bit5 bit0
bit7
bit0
PWM register (high-order) (address 001416) PWM latch (14-bit)
MSB LSB
14
P87 latch P87/PWM0 PWM P87/PWM output selection bit P87/PWM output selection bit P87 direction register
14-bit PWM circuit
XCIN When an internal 1/2 system clock selection bit is set (64 s cycle) Timing "1" to "0" generating unit for PWM (4096 s cycle) "0"
XIN (4MHz)
Fig. 56 PWM block diagram
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HARDWARE
FUNCTIONAL DESCRIPTION
1. Data setup The PWM output pin also function as port P87. Set port P87 to be the PWM output pin by setting bit 0 of the PWM control register (address 002616) to "1." The high-order 8 bits of output data are set in the high-order PWM register PWMH (address 001416) and the low-order 6 bits are set in the low-order PWM register PWML (address 001516). 2. PWM operation The timing of the 14-bit PWM function is shown in Figure 57. The 14-bit PWM data is divided into the low-order 6 bits and the high-order 8 bits in the PWM latch. The high-order 8 bits of data determine how long an "H" level signal is output during each sub-period. There are 64 sub-periods in each period, and each sub-period t is 256 ! (= 64 s) long. The signal's "H" has a length equal to N times , and its minimum resolution = 250 ns. The last bit of the sub-period becomes the ADD bit which is specified either "H" or "L," by the contents of PWML. As shown in Table 10, the ADD bit is decided either "H" or "L." That is, only in the sub-period tm shown in Table 10 in the PWM cycle period T = 64t, the "H" duration is lengthened during the minimum resolution width period in comparison with the other period. For example, if the high-order eight bits of the 14-bit data are "0316" and the low-order six bits are "0516," the length of the "H" level output in sub-periods t8, t24, t32, t40 and t56 is 4 , and its length 3 in all other sub-periods. Time at the "H" level of each sub-period almost becomes equal because the time becomes length set in the high-order 8 bits or becomes the value plus , and this sub-period t (= 64 s, approximate 15.6 kHz) becomes cycle period approximately. 3. Transfer from register to latch Data written to the PWML register is transferred to the PWM latch once in each PWM period (every 4096 s), and data written to the PWMH register is transferred to the PWM latch once in each subperiod (every 64 s). When the PWML register is read, the contents of the latch are read. However, bit 7 of the PWML register indicates whether the transfer to the PWM latch is completed; the transfer is completed when bit 7 is "0." Table 10 Relationship between low-order 6-bit data and setting period of ADD bit Low-order Sub-periods tm lengthened (m = 0 to 63) 6-bit data
LSB
000000 000001 000010 000100 001000 010000 100000
None m = 32 m = 16, 48 m = 8, 24, 40, 56 m = 4, 12, 20, 28, 36, 44, 52, 60 m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62 m = 1, 3, 5, 7, .................................................., 57, 59, 61, 63
4096 s 64 s m=0 64 s m=7 64 s m=8 64 s m=9 64 s m = 63
15.75 s
15.75 s
15.75 s
16.0 s
15.75 s
15.75 s
15.75 s
Pulse width modulation register H: 00111111 Pulse width modulation register L: 000101 Sub-periods where "H" pulse width is 16.0 s: m = 8, 24, 32, 40, 56 Sub-periods where "H" pulse width is 15.75 s: m = all other values
Fig. 57 PWM timing
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FUNCTIONAL DESCRIPTION
b7
b0 PWM control register (PWMCON: address 002616) P87/PWM output selection bit 0: I/O port 1: PWM output Not used (return "0" when read)
Fig. 58 Structure of PWM control register
Data 6A16 stored at address 001416 PWM register (high-order) 5916 6A16 Bit 7 cleared after transfer 2416 Transfer from register to latch PWM latch (14-bit) 165316 1A9316 1AA416 T = 4096 s (64 ! 64 s) t = 64 s 1AA416
Data 7B16 stored at address 001416 7B16 Data 3516 stored at address 001516 3516 B516 1EE416 Transfer from register to latch 1EF516
Data 2416 stored at address 001516 PWM register (low-order) 1316 A416
When bit 7 of PWML is "0," transfer from register to latch is disabled.
(Example 1) PWM output 1 Low-order 6-bits output H = 6A16 L = 2416
6A
6B
6A
6B
6A
6B
6A
6B
6A
6B
6B
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
5
5
5
5
5
2
5
5
5
5 106 ! 64 + 36
5
5
5
5
5
6B16............36 times (107)
6A16............28 times (106)
(Example 2) PWM output
6A
6A
6A
6A
6B
6A
6B
6A
6B
6A
6A
6A
6B
6A
6B
6A
6B
6A
6A
6A
6B
6A
6B
6A
6B
6A
6A
Low-order 6 bits output H = 6A16 L = 1816
4
3
4
4 6A16............40 times
3
4 106 ! 64 + 24
4
3
4
6B16............24 times
t = 64 s (256 ! 0.25 s) Minimum bit width
= 0.25 s
6A 69 68 67
.........
PWM output 2
6B ADD
02
01 ADD
6A
69
68
67
..........
02
01
8-bit counter
02
01
00
FF
FE
FD
FC
..........
97
96
95
..........
02
01
00
FF
FE
FD
FC
..........
97
96
95
............
The ADD portions with additional are determined either "H" or "L" by low-order 6-bit data.
"H" period length specified by PWMH
256
(64 s), fixed
Fig. 59 14-bit PWM timing
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HARDWARE
FUNCTIONAL DESCRIPTION
Interrupt Interval Determination Function
The 38B5 group has an interrupt interval determination circuit. This interrupt interval determination circuit has an 8-bit binary up counter. Using this counter, it determines a duration of time from the rising edge (falling edge) of an input signal pulse on the P47/INT2 pin to the rising edge (falling edge) of the signal pulse that is input next. How to determine the interrupt interval is described below. 1. Enable the INT2 interrupt by setting bit 2 of the interrupt control register 1 (address 003E16). Select the rising interval or falling interval by setting bit 2 of the interrupt edge selection register (address 003A16). 2. Set bit 0 of the interrupt interval determination control register (address 003116) to "1" (interrupt interval determination operating). 3. Select the sampling clock of 8-bit binary up counter by setting bit 1 of the interrupt interval determination control register. When writing "0," f(XIN)/128 is selected (the sampling interval: 32 s at f(XIN) = 4.19 MHz); when "1," f(XIN)/256 is selected (the sampling interval: 64 s at f(XIN) = 4.19 MHz). 4. When the signal of polarity which is set on the INT2 pin (rising or falling edge) is input, the 8-bit binary up counter starts counting up of the selected counter sampling clock. 5. When the signal of polarity above 4 is input again, the value of the 8-bit binary up counter is transferred to the interrupt interval determination register (address 003016), and the remote control interrupt request occurs. Immediately after that, the 8-bit binary up counter continues to count up again from "0016." 6. When count value reaches "FF16," the 8-bit binary up counter stops counting up. Then, simultaneously when the next counter sampling clock is input, the counter sets value "FF16" to the interrupt interval determination register to generate the counter overflow interrupt request. Noise filter The P47/INT2 pin builds in the noise filter. The noise filter operation is described below. 1. Select the sampling clock of the input signal with bits 2 and 3 of the interrupt interval determination control register. When not using the noise filter, set "00." 2. The P47/INT2 input signal is sampled in synchronization with the selected clock. When sampling the same level signal in a series of three sampling, the signal is recognized as the interrupt signal, and the interrupt request occurs. When setting bit 4 of interrupt interval determination control register to "1," the interrupt request can occur at both rising and falling edges. When using the noise filter, set the minimum pulse width of the INT2 input signal to 3 cycles or more of the sample clock. Note: In the low-speed mode (CM7 = 1), the interrupt interval determination function cannot operate.
Counter sampling clock selection bit
f(XIN)/128 f(XIN)/256
8-bit binary up counter
Counter overflow interrupt request or remote control interrupt request
INT2 interrupt input
Noise filter
Interrupt interval determination register
address 003016
Noise filter sampling clock selection bit 1/32 1/64
One-sided/both-sided detection selection bit 1/128
Data bus
Divider
f(XIN)
Fig. 60 Interrupt interval determination circuit block diagram
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FUNCTIONAL DESCRIPTION
b7
b0
Interrupt interval determination control register (IIDCON: address 003116) Interrupt interval determination circuit operating selection bit 0 : Stopped 1 : Operating Counter sampling clock selection bit 0 : f(XIN)/128 1 : f(XIN)/256 Noise filter sampling clock selection bits (INT2) 00 : Filter stop 01 : f(XIN)/32 10 : f(XIN)/64 11 : f(XIN)/128 One-sided/both-sided edge detection selection bit 0 : One-sided edge detection 1 : Both-sided edge detection (can be used when using a noise filter) Not used (return "0" when read)
Fig. 61 Structure of interrupt interval determination control register
(When IIDCON4 = "0") Noise filter sampling clock INT2 pin
Acceptance of interrupt
Counter sampling clock N 8-bit binary up counter value N Interrupt interval determination register value N Remote control interrupt request Remote control interrupt request 0 1 2 3 4 6 0 6 6 Counter overflow interrupt request 1 2 3 0 FF FF FE FF 1
5
Fig. 62 Interrupt interval determination operation example (at rising edge active)
(When IIDCON4 = "1") Noise filter sampling clock INT2 pin
Acceptance of interrupt
Counter sampling clock N 8-bit binary up counter value N Interrupt interval determination register value N Remote control interrupt request Remote control interrupt request 0 1 2 0 2 2 1 2 3 0 3 3 Remote control interrupt request Remote control interrupt request 1 2 0 2 2 1 2 FE FF 0 FF FF Counter overflow interrupt request 1
Fig. 63 Interrupt interval determination operation example (at both-sided edge active)
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HARDWARE
FUNCTIONAL DESCRIPTION
Watchdog Timer
The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software runaway). The watchdog timer consists of an 8-bit watchdog timer L and a 12-bit watchdog timer H. qStandard operation of watchdog timer When any data is not written into the watchdog timer control register (address 002B16) after resetting, the watchdog timer is in the stop state. The watchdog timer starts to count down by writing an optional value into the watchdog timer control register (address 002B16) and an internal reset occurs at an underflow of the watchdog timer H. Accordingly, programming is usually performed so that writing to the watchdog timer control register (address 002B16) may be started before an underflow. When the watchdog timer control register (address 002B16) is read, the values of the high-order 6 bits of the watchdog timer H, STP instruction disable bit, and watchdog timer H count source selection bit are read. (1) Initial value of watchdog timer At reset or writing to the watchdog timer control register (address 002B16), a watchdog timer H is set to "FFF16" and a watchdog timer L to "FF16." (2) Watchdog timer H count source selection bit operation Bit 7 of the watchdog timer control register (address 002B16) permits selecting a watchdog timer H count source. When this bit is set to "0," the underflow signal of watchdog timer L becomes the count source. The detection time is set then to f(XIN) = 2.1 s at 4 MHz frequency and f(XCIN) = 512 s at 32 kHz frequency. When this bit is set to "1," the count source becomes the signal divided by 8 for f(XIN) (or divided by 16 for f(XCIN)). The detection time in this case is set to f(XIN) = 8.2 ms at 4 MHz frequency and f(XCIN) = 2 s at 32 KHz frequency. This bit is cleared to "0" after resetting. (3) Operation of STP instruction disable bit Bit 6 of the watchdog timer control register (address 002B16) permits disabling the STP instruction when the watchdog timer is in operation. When this bit is "0," the STP instruction is enabled. When this bit is "1," the STP instruction is disabled. Once the STP instruction is executed, an internal resetting occurs. When this bit is set to "1," it cannot be rewritten to "0" by program. This bit is cleared to "0" after resetting.
s Note
When releasing the stop mode, the watchdog timer performs its count operation even in the stop release waiting time. Be careful not to cause the watchdog timer H to underflow in the stop release waiting time, for example, by writing data in the watchdog timer control register (address 002B16) before executing the STP instruction.
XCIN
1/2 "1" Internal system clock selection bit (Note)
"FF16" is set when watchdog timer control register is written to. "0" Watchdog timer L (8) 1/8 "0" "1" Watchdog timer H (12)
Data bus "FFF16" is set when watchdog timer control register is written to.
XIN
Watchdog timer H count source selection bit
STP instruction disable bit STP instruction Reset circuit Internal reset
RESET
Note: Either high-speed, middle-speed or low-speed mode is selected by bit 7 of CPU mode register.
Fig. 64 Block diagram of watchdog timer
b7
b0
Watchdog timer control register (WDTCON : address 002B16)
Watchdog timer H (for read-out of high-order 6 bit) STP instruction disable bit 0: STP instruction enabled 1: STP instruction disabled Watchdog timer H count source selection bit 0: Watchdog timer L underflow 1: f(XIN)/8 or f(XCIN)/16
Fig. 65 Structure of watchdog timer control register
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FUNCTIONAL DESCRIPTION
Buzzer Output Circuit
The 38B5 group has a buzzer output circuit. One of 1 kHz, 2 kHz and 4 kHz (at XIN = 4.19 MHz) frequencies can be selected by the buzzer output control register (address 0EFD16). Either P43/BUZ01 or P20/ BUZ02/FLD0 can be selected as a buzzer output port by the output port selection bits (b2 and b3 of address 0EFD16). The buzzer output is controlled by the buzzer output ON/OFF bit (b4).
Port latch f(XIN)
1/1024 1/2048 1/4096
Divider
Buzzer output
Buzzer output ON/OFF bit Output port control signal Port direction register
Fig. 66 Block diagram of buzzer output circuit
b7
b0
Buzzer output control register (BUZCON: address 0EFD16) Output frequency selection bits (XIN = 4.19 MHz) 00 : 1 kHz (f(XIN)/4096) 01 : 2 kHz (f(XIN)/2048) 10 : 4 kHz (f(XIN)/1024) 11 : Not available Output port selection bits 00 : P20 and P43 function as ordinary ports. 01 : P43/BUZ01 functions as a buzzer output. 10 : P20/BUZ02/FLD0 functions as a buzzer output. 11 : Not available Buzzer output ON/OFF bit 0 : Buzzer output OFF ("0" output) 1 : Buzzer output ON Not used (return "0" when read)
Fig. 67 Structure of buzzer output control register
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HARDWARE
FUNCTIONAL DESCRIPTION
Reset Circuit
______
To reset the microcomputer, RESET pin should be held at an "L" ______ level for 2 s or more. Then the RESET pin is returned to an "H" level (the power source voltage should be between 2.7 V and 5.5 V, and the oscillation should be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.5 V for VCC of 2.7 V (switching to the high-speed mode, a power source voltage must be between 4.0 V and 5.5 V).
Poweron Power source voltage 0V Reset input voltage 0V (Note)
RESET
VCC
0.2VCC
Note : Reset release voltage ; Vcc=2.7 V
RESET
VCC Power source voltage detection circuit
Fig. 68 Reset circuit example
XIN
RESET Internal reset
Address
?
?
?
?
FFFC
FFFD
ADH, ADL
Data
ADL
ADH
SYNC
XIN: about 4000 cycles Notes 1: The frequency relation of f(XIN) and f() is f(XIN)=4 * f(). 2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 69 Reset sequence
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FUNCTIONAL DESCRIPTION
Address Register contents (1) Port P0 (2) Port P0 direction register (3) Port P1 (4) Port P2 (5) Port P2 direction register (6) Port P3 (7) Port P4 (8) Port P4 direction register (9) Port P5 (10) Port P5 direction register (11) Port P6 (12) Port P6 direction register (13) Port P7 (14) Port P7 direction register (15) Port P8 (16) Port P8 direction register (17) Port P9 (18) Port P9 direction register (19) UART control register (20) Serial I/O1 control register 1 (21) Serial I/O1 control register 2 (22) Serial I/O1 control register 3 (23) Serial I/O2 control register (24) Serial I/O2 status register (25) Timer 1 (26) Timer 2 (27) Timer 3 (28) Timer 4 (29) Timer 5 (30) Timer 6 (31) PWM control register (32) Timer 12 mode register 000016 000116 000216 000416 000516 000616 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001716 001916 001A16 001C16 001D16 001E16 002016 002116 002216 002316 002416 002516 002616 002816 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 8016 0016 0016 0016 0016 8016 FF16 0116 FF16 FF16 FF16 FF16 0016 0016 (33) Timer 34 mode register (34) Timer 56 mode register (35) Watchdog timer control register (36) Timer X (low-order) (37) Timer X (high-order) (38) Timer X mode register 1 (39) Timer X mode register 2 (40) Interrupt interval determination control register (41) A-D control register (42) Interrupt source switch register (43) Interrupt edge selection register (44) CPU mode register (45) Interrupt request register 1 (46) Interrupt request register 2 (47) Interrupt control register 1 (48) Interrupt control register 2 (49) Pull-up control register 1 (50) Pull-up control register 2
Address Register contents 002916 002A16 002B16 002C16 002D16 002E16 002F16 003116 003216 003916 003A16 0016 0016 3F16 FF16 FF16 0016 0016 0016 1016 0016 0016
003B16 0 1 0 0 1 0 0 0 003C16 003D16 003E16 003F16 0EF016 0EF116 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 FF16 FF16 0016 0016 0016 0016 0016
(51) P1FLDRAM write disable register 0EF216 (52) P3FLDRAM write disable register 0EF316 (53) FLDC mode register (54) Tdisp time set register (55) Toff1 time set register (56) Toff2 time set register (57) Port P0FLD/port switch register (58) Port P2FLD/port switch register (59) Port P8FLD/port switch register (60) Port P8FLD output control register (61) Buzzer output control register (62) Processor status register (63) Program counter 0EF416 0EF516 0EF616 0EF716 0EF916 0EFA16 0EFB16 0EFC16 0EFD16
(PS) ! ! ! ! ! 1 ! ! (PCH) (PCL)
FFFD16 contents FFFC16 contents
!: Not fixed Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set.
Fig. 70 Internal status at reset
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HARDWARE
FUNCTIONAL DESCRIPTION
Clock Generating Circuit
The 38B5 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feedback resistor exists on-chip. However, an external feedback resistor is needed between XCIN and XCOUT. Immediately after power on, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports.
qOscillation control
(1) Stop mode If the STP instruction is executed, the internal system clock stops at an "H" level, and XIN and XCIN oscillators stop. Timer 1 is set to "FF16" and timer 2 is set to "0116." Either XIN divided by 8 or XCIN divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. The bits of the timer 12 mode register are cleared to "0." Set the interrupt enable bits of the timer 1 and timer 2 to disabled ("0") before executing the STP instruction. Oscillator restarts when an external interrupt is received, but the internal system clock is not supplied to the CPU until timer 1 underflows. This allows time for the clock circuit oscillation to stabilize. (2) Wait mode If the WIT instruction is executed, the internal system clock stops at an "H" level. The states of XIN and XCIN are the same as the state before executing the WIT instruction. The internal system clock restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted.
qFrequency control
(1) Middle-speed mode The internal system clock is the frequency of XIN divided by 4. After reset, this mode is selected. (2) High-speed mode The internal system clock is the frequency of XIN. (3) Low-speed mode The internal system clock is the frequency of XCIN divided by 2. sNote If you switch the mode between middle/high-speed and low-speed, stabilize both XIN and XCIN oscillations. The sufficient time is required for the sub clock to stabilize, especially immediately after power on and at returning from stop mode. When switching the mode between middle/high-speed and low-speed, set the frequency on condition that f(XIN) > 3f(XCIN). (4) Low power consumption mode The low power consumption operation can be realized by stopping the main clock XIN in low-speed mode. To stop the main clock, set bit 5 of the CPU mode register to "1." When the main clock XIN is restarted (by setting the main clock stop bit to "0"), set enough time for oscillation to stabilize. By clearing furthermore the XCOUT drivability selection bit (b3) of CPU mode register to "0," low power consumption operation of less than 200 A (f(XCIN) = 32 kHz) can be realized by reducing the drivability between XCIN and XCOUT. At reset or during STP instruction execution this bit is set to "1" and a strong drivability that has an easy oscillation start is set.
XCIN Rf
XCOUT Rd CCOUT
XIN
XOUT
CCIN
CIN
COUT
Fig. 71 Ceramic resonator circuit
XCIN
XCOUT open
XIN
XOUT
open External oscillation circuit VCC VSS
External oscillation circuit or external pulse VCC VSS
Fig. 72 External clock input circuit
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FUNCTIONAL DESCRIPTION
XCIN
XCOUT
"1"
"0"
Port XC switch bit (Note 3)
1/2 XIN XOUT
Internal system clock selection bit (Notes 1, 3) Low-speed mode
"1"
Timer 1 count source selection bit (Note 2)
"1"
Timer 2 count source selection bit (Note 2)
"0"
Timer 1 1/4 1/2
"0"
Timer 2
"1"
"0"
High-speed or middle-speed mode Main clock division ratio selection bits (Note 3) Middle-speed mode
"1" "0"
Timing (internal clock)
Main clock stop bit (Note 3)
High-speed or low-speed mode
Q
S R
STP instruction WIT instruction
SQ R
QS R
STP instruction
Reset Interrupt disable flag l Interrupt request
Notes 1: When low-speed mode is selected, set the port Xc switch bit (b4) to "1." 2: Refer to the structure of the timer 12 mode register. 3: Refer to the structure of the CPU mode register.
Fig. 73 Clock generating circuit block diagram
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HARDWARE
FUNCTIONAL DESCRIPTION
Reset
Middle-speed mode ( =1 MHz) CM7=0(4 MHz selected) CM6=1(middle-speed) CM5=0(XIN oscillating) CM4=0(32 kHz stopped)
CM6 "1"
High-speed mode ( =4 MHz)
"0"
CM7=0(4 MHz selected) CM6=0(high-speed) CM5=0(XIN oscillating) CM4=0(32 kHz stopped)
"0"
4 "0" CM 6 0" " M" "1 C " "1
CM4
"0 "1 "
" CM 4 CM "1 6 " "0 "
CM4
High-speed mode ( =4 MHz) CM7=0(4 MHz selected) CM6=0(high-speed) CM5=0(XIN oscillating) CM4=1(32 kHz oscillating)
Middle-speed mode ( =1 MHz) CM7=0(4 MHz selected) CM6=1(middle-speed) CM5=0(XIN oscillating) CM4=1(32 kHz oscillating)
"1"
CM6 "1" "0"
CM7
"0"
CM7 "1" CM6 "1" "0"
Low-speed mode ( =16 kHz) CM7=1(32 kHz selected) CM6=0(high-speed) CM5=0(XIN oscillating) CM4=1(32 kHz oscillating)
Low-speed mode ( =16 kHz) CM7=1(32 kHz selected) CM6=1(middle-speed) CM5=0(XIN oscillating) CM4=1(32 kHz oscillating)
"1"
"0"
"1"
"0"
b7
b4 CPU mode register (CPUM : address 003B 16)
CM4 : Port Xc switch bit 0: I/O port function 1: XCIN-XCOUT oscillating function CM5 : Main clock (XIN- XOUT) stop bit 0: Oscillating 1: Stopped CM6: Main clock division ratio selection bit 0: f(XIN) (High-speed mode) 1: f(XIN)/4 (Middle-speed mode) CM7: Internal system clock selection bit 0: XIN-XOUT selected (Middle-/High-speed mode) 1: XCIN-XCOUT selected (Low-speed mode)
"0"
CM5
"1"
"
Low-power dissipation mode ( =16 kHz) CM7=1(32 kHz selected) CM6=1(middle-speed) CM5=1(XIN stopped) CM4=1(32 kHz oscillating)
CM6 "1" "0"
Low-power dissipation mode ( =16 kHz) CM7=1(32 kHz selected) CM6=0(high-speed) CM5=1(XIN stopped) CM4=1(32 kHz oscillating)
Notes 1: Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.) 2: The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3: Timer operates in the wait mode. 4: When the stop mode is ended, a delay of approximately 1 ms occurs by Timer 1 in middle-/high-speed mode. 5: When the stop mode is ended, a delay of approximately 0.25 s occurs by Timer 1 in low-speed mode. 6: The example assumes that 4 MHz is being applied to the X IN pin and 32 kHz to the X CIN pin. indicates the internal system clock.
Fig. 74 State transitions of system clock
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38B5 Group User's Manual
"1"
"1
"
CM 1"
6
"0
"
"1
"
CM5
C
M
"0
5
"
"0
" CM 5 CM "1 6 " "0 "
"0"
HARDWARE
NOTES ON PROGRAMMING/NOTES ON USE
NOTES ON PROGRAMMING Processor Status Register
The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is "1." After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations.
A-D Converter
The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Therefore, make sure that f(XIN) is at least on 250 kHz during an A-D conversion. Do not execute the STP or WIT instruction during an A-D conversion.
Interrupts
The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction.
Instruction Execution Time
The instruction execution time is obtained by multiplying the frequency of the internal system clock by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal system clock is the same of the XIN frequency in high-speed mode.
Decimal Calculations
*To calculate in decimal notation, set the decimal mode flag (D) to "1," then execute an ADC or SBC instruction. Only the ADC and SBC instructions yield proper decimal results. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. *In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid.
At STP Instruction Release
At the STP instruction release, all bits of the timer 12 mode register are cleared. The XCOUT drivability selection bit (the CPU mode register) is set to "1" (high drive) in order to start oscillating.
Timers
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
NOTES ON USE Notes on Built-in EPROM Version
The P47 pin of the One Time PROM version or the EPROM version functions as the power source input pin of the internal EPROM. Therefore, this pin is set at low input impedance, thereby being affected easily by noise. To prevent a malfunction due to noise, insert a resistor (approx. 5 k) in series with the P47 pin.
Multiplication and Division Instructions
*The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. *The execution of these instructions does not change the contents of the processor status register.
Ports
The contents of the port direction registers cannot be read. The following cannot be used: *The data transfer instruction (LDA, etc.) *The operation instruction when the index X mode flag (T) is "1" *The addressing mode which uses the value of a direction register as an index *The bit-test instruction (BBC or BBS, etc.) to a direction register *The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers.
Serial I/O
*Using an external clock When using an external clock, input "H" to the external clock input pin and clear the serial I/O interrupt request bit before executing serial I/O transfer and serial I/O automatic transfer. *Using an internal clock When using an internal clock, set the synchronous clock to the internal clock, then clear the serial I/O interrupt request bit before executing a serial I/O transfer and serial I/O automatic transfer.
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HARDWARE
DATA REQUIRED FOR MASK ORDERS/DATA REQUIRED FOR ROM WRITING ORDERS/ROM PROGRAMMING METHOD
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production: (1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (three identical copies)
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and the EPROM version can be read or programmed with a general purpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area. Table 11 Special programming adapter Package 80P6N-A 80D0 Name of Programming Adapter PCA7438F-80A PCA7438L-80A
DATA REQUIRED FOR ROM WRITING ORDERS
The following are necessary when ordering a ROM writing: (1) ROM Writing Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (three identical copies)
The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 75 is recommended to verify programming.
Programming with PROM programmer
Screening (Note) (150C for 40 hours)
Verification with PROM programmer
Functional check in target device Note: The screening temperature is far higher than the storage temperature. Never expose to 150 C exceeding 100 hours.
Fig. 75 Programming and testing of One Time PROM version
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HARDWARE
MASK OPTION OF PULL-DOWN RESISTOR
MASK OPTION OF PULL-DOWN RESISTOR (object product: M38B5XMXH-XXXFP)
Whether built-in pull-down resistors are connected or not to highbreakdown voltage ports P20 to P27 and P80 to P83 can be specified in ordering mask ROM. The option type can be specified from among 8 types; A to G, P as shown Table 12. Table 12 Mask option type of pull-down resistor
Option type Connective port of pull-down resistor Restriction (connected at "1" writing) P20 P21 P22 P23 P24 P25 P26 P27 P80 P81 P82 P83 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Power Dissipation Calculating example 1
q Fixed number depending on microcomputer's standard * VOH output fall voltage of high-breakdown port 2 V (max.); | Current value | = at 18 mA * Resistor value 43 V / 900 A = 48 k (min.) * Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V ! 15 mA = 75 mW q Fixed number depending on use condition * Apply voltage to VEE pin: Vcc - 45 V * Timing number 17; digit number 16; segment number 20 * Ratio of Toff time corresponding Tdisp time: 1/16 * Turn ON segment number during repeat cycle: 31 * All segment number during repeat cycle: 340 (= 17 ! 20) * Total number of built-in resistor: for digit; 16, for segment; 20 * Digit pin current value: 18 (mA) * Segment pin current value: 3 (mA) (1) Digit pin power dissipation {18 ! 16 ! (1-1/16) ! 2} / 17 = 31.77 mW (2) Segment pin power dissipation {3 ! 31 ! (1-1/16) ! 2} / 17 = 10.26 mW (3) Pull-down resistor power dissipation (digit) (45 - 2)2 /48 ! (16 ! 16/16) ! (1 - 1/16) / 17 = 33.99 mW (4) Pull-down resistor power dissipation (segment) (45 - 2)2 /48 ! (31 ! 20/20) ! (1 - 1/16) / 17 = 65.86 mW (5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 75 mW (1) + (2)+ (3) + (4) + (5) = 217 mW
A ($41) B ($42) C ($43) D ($44) E ($45) 1 F ($46) 1 G ($47) 1 P ($50) 1
1 1 1 1
1 1 1 1 1
1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1 1
1 1
1
1 (Note 4)
Notes 1: The electrical characteristics of high-breakdown voltage ports P20 to P27 and P80 to P83's built-in pull-down resistors are the same as that of high-breakdown voltage ports P00 to P07. 2: The absolute maximum ratings of power dissipation may be exceed owing to the number of built-in pull-down resistor. After calculating the power dissipation, specify the option type. 3: One time PROM version and EPROM version cannot be specified whether built-in pull-down resistors are connected or not likewise option type A. 4: INT3 function and CNTR1 function cannot be used in the option type P.
Power Dissipation Calculating Method
q Fixed number depending on microcomputer's standard * VOH output fall voltage of high-breakdown port 2 V (max.); | Current value | = at 18 mA * Resistor value 43 V / 900 A = 48 k (min.) * Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V ! 15 mA = 75 mW q Fixed number depending on use condition * Apply voltage to VEE pin: Vcc - 45 V * Timing number a; digit number b; segment number c * Ratio of Toff time corresponding Tdisp time: 1/16 * Turn ON segment number during repeat cycle: d * All segment number during repeat cycle: c (= a ! c) * Total number of built-in resistor: for digit; f, for segment; g * Digit pin current value h (mA) * Segment pin current value i (mA) (1) Digit pin power dissipation {h ! b ! (1-Toff/Tdisp) ! voltage} / a (2) Segment pin power dissipation {i ! d ! (1-Toff/Tdisp) ! voltage} / a (3) Pull-down resistor power dissipation (digit) {power dissipation per 1 digit ! (b ! f / b) ! (1-Toff/Tdisp) } / a (4) Pull-down resistor power dissipation (segment) {power dissipation per 1 segment ! (d ! g / c) ! (1-Toff/Tdisp) } / a (5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 75 mW (1) + (2)+ (3) + (4) + (5) = X mW
DIG0 DIG1 DIG2 DIG3
DIG14 DIG15 DIG16 Timing number 1 2 3 Repeat cycle Tscan 14 15 16 17
Fig. 76 Digit timing waveform (1)
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MASK OPTION OF PULL-DOWN RESISTOR
Power Dissipation Calculating example 2 (when 2 or more digit is turned ON at same time)
q Fixed number depending on microcomputer's standard * VOH output fall voltage of high-breakdown port 2 V (max.); | Current value | = at 18 mA * Resistor value 43 V / 900 A = 48 k (min.) * Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V ! 15 mA = 75 mW q Fixed number depending on use condition * Apply voltage to VEE pin: Vcc - 45 V * Timing number 11; digit number 12; segment number 24 * Ratio of Toff time corresponding Tdisp time: 1/16 * Turn ON segment number during repeat cycle: 114 * All segment number during repeat cycle: 264 (= 11 ! 24) * Total number of built-in resistor: for digit; 10, for segment; 22 * Digit pin current value: 18 (mA) * Segment pin current value: 3 (mA) (1) Digit pin power dissipation {18 ! 12 ! (1-1/16) ! 2} / 11 = 36.82 mW (2) Segment pin power dissipation {3 ! 114 ! (1-1/16) ! 2} / 11 = 58.30 mW (3) Pull-down resistor power dissipation (digit) (45 - 2)2 /48 ! (12 ! 10/12) ! (1 - 1/16) / 11 = 32.84 mW (4) Pull-down resistor power dissipation (segment) (45 - 2)2 /48 ! (114 ! 22/24) ! (1 - 1/16) / 11 = 343.08 mW (5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 75 mW (1) + (2)+ (3) + (4) + (5) = 547 mW
DIG0 DIG1 DIG2 DIG3 DIG4 DIG5 DIG6 DIG7 DIG8 DIG9 Timing number 1 2 3 4 5 6 7 8 9 10 11
Repeat cycle Tscan
Fig. 77 Digit timing waveform (2)
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HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
FUNCTIONAL DESCRIPTION SUPPLEMENT Interrupt
38B5 group permits interrupts on the basis of 21 sources. It is vector interrupts with a fixed priority system. Accordingly, when two or more interrupt requests occur during the same sampling, the Table 13 Interrupt sources, vector addresses and interrupt priority Interrupt source Reset (Note 2) INT0 INT1 INT2 Remote control/counter overflow Serial I/O1 Serial I/O1 automatic transfer Timer X Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 Timer 6 Serial I/O2 receive INT3 Serial I/O2 transmit INT4 A-D conversion FLD blanking FLD digit BRK instruction Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Vector Addresses (Note 1) High Low FFFD16 FFFC16 FFFB16 FFF916 FFF716 FFF516 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFE116 FFFA16 FFF816 FFF616 FFF416 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when interrupt interval determination is operating Valid when serial I/O1 ordinary mode is selected Valid when serial I/O1 automatic transfer mode is selected higher-priority interrupt is accepted first. This priority is determined by hardware, but various priority processing can be performed by software, using an interrupt enable bit and an interrupt disable flag. For interrupt sources, vector addresses and interrupt priority, refer to Table 13.
STP release timer underflow (Note 3)
External interrupt (active edge selectable) (Note 4) External interrupt (active edge selectable) Valid when INT4 interrupt is selected Valid when A-D conversion is selected Valid when FLD blanking interrupt is selected Valid when FLD digit interrupt is selected Non-maskable software interrupt
16
FFDF16
FFDE16
17 FFDD16 FFDC16 Notes 1 : Vector addresses contain interrupt jump destination addresses. 2 : Reset function in the same way as an interrupt with the highest priority. 3 : In the mask option type P, timer 4 interrupt whose count source is CNTR1 input cannot be used. 4 : In the mask option type P, INT3 interrupt cannot be used.
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HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
Timing After Interrupt
The interrupt processing routine begins with the machine cycle following the completion of the instruction that is currently in execution. Figure 78 shows a timing chart after an interrupt occurs, and Figure 79 shows the time up to execution of the interrupt processing routine.
SYNC RD WR Address bus Data bus
PC Not used
S, SPS
S-1, SPS S-2, SPS
BL AL
BH
AL, AH AH
PCH
PCL
PS
SYNC : CPU operation code fetch cycle (This is an internal signal which cannot be observed from the external unit.) BL, BH : Vector address of each interrupt AL, AH : Jump destination address of each interrupt SPS : "0016" or "0116"
Fig. 78 Timing chart after interrupt occurs
Interrupt request occurs
Interrupt operation starts
Main routine
Waiting time for pipeline postprocessing
Push onto stack vector fetch
Interrupt processing routine
0 to 16 cycles
2 cycles
5 cycles
7 to 23 cycles (4 MHz, 1.75 s to 5.75 s)
Fig. 79 Time up to execution of interrupt processing routine
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HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
A-D Converter
A-D conversion is started by setting AD conversion completion bit to "0." During A-D conversion, internal operations are performed as follows. 1. After the start of A-D conversion, A-D conversion register goes to "0016." 2. The highest-order bit of A-D conversion register is set to "1," and the comparison voltage Vref is input to the comparator. Then, Vref is compared with analog input voltage VIN. 3. As a result of comparison, when Vref < VIN, the highest-order bit of A-D conversion register becomes "1." When Vref > VIN, the highest-order bit becomes "0." By repeating the above operations up to the lowest-order bit of the A-D conversion register, an analog value converts into a digital value. A-D conversion completes at 61 clock cycles (15.25 s at f(XIN) = 8 MHz) after it is started, and the result of the conversion is stored into the A-D conversion register. Concurrently with the completion of A-D conversion, A-D conversion interrupt request occurs, so that the AD conversion interrupt request bit is set to "1."
Table 14 Relative formula for a reference voltage VREF of A-D converter and Vref When n = 0 Vref = 0 VREF When n = 1 to 1023 Vref = !n 1024 n: Value of A-D converter (decimal numeral) Table 15 Change of A-D conversion register during A-D conversion Change of A-D conversion register At start of conversion First comparison Second comparison Third comparison Value of comparison voltage (Vref)
0 1
V1
0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
VREF 2 VREF 2 VREF 2
0
VREF 4 VREF 4 VREF 8
V1 V2
After completion of tenth comparison
A result of A-D conversion
V1 V2 V3 V4 V5 V6 V7 V8 V9 V 0 1
VREF 2
VREF 4
****
VREF 1024
V1-V10: A result of the first comparison to the tenth comparison
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FUNCTIONAL DESCRIPTION SUPPLEMENT
Figures 80 shows the A-D conversion equivalent circuit, and Figure 81 shows the A-D conversion timing chart.
VCC About 2 k AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11
VSS VIN
Sampling clock
VCC
VSS
C
Chopper amplifier A-D conversion register (high-order)
A-D conversion register (low-order) AD conversion interrupt request
b3 b2 b1 b0 A-D control register
VREF
Built-in D-A converter
Vref
Reference clock
VSS
Fig. 80 A-D conversion equivalent circuit
Write signal for A-D control register
61 cycles
AD conversion completion bit Sampling clock
Fig. 81 A-D conversion timing chart
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CHAPTER 2 APPLICATION
I/O port Timer Serial I/O FLD controller A-D converter PWM Interrupt interval determination function 2.8 Watchdog timer 2.9 Buzzer output circuit 2.10 Reset circuit 2.11 Clock generating circuit 2.1 2.2 2.3 2.4 2.5 2.6 2.7
APPLICATION
2.1 I/O port
2.1 I/O port
This paragraph describes the setting method of I/O port relevant registers, notes etc. 2.1.1 Memory assignment
Address 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) Port P7 (P7) Port P7 direction register (P7D) Port P8 (P8) Port P8 direction register (P8D) Port P9 (P9) Port P9 direction register (P9D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1)
0EF016 0EF116
Pull-up control register 1 (PULL1) Pull-up control register 2 (PULL2)
Fig. 2.1.1 Memory assignment of I/O port relevant registers
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APPLICATION
2.1 I/O port
2.1.2 Relevant registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0 Port Pi (i = 0, 1, 2, 3, 4, 5, 7, 8) (Pi: addresses 0016, 0216, 0416, 0616, 0816, 0A16, 0E16, 1016)
b
0 1 2 3 4 5 6 7
Name
Port Pi0 Port Pi1 Port Pi2 Port Pi3 Port Pi4 Port Pi5 Port Pi6 Port Pi7
Functions
qIn output mode Write ******** Port latch Read ******** Port latch qIn input mode Write ******** Port latch Read ******** Value of pin
At reset R W
0 0 0 0 0 0 0 0
Fig. 2.1.2 Structure of port Pi (i = 0, 1, 2, 3, 4, 5, 7, 8)
Port P6
b7 b6 b5 b4 b3 b2 b1 b0 Port P6 (P6: address 0C16)
b
0 1 2 3 4 5 6 7
Name
Functions
At reset R W
0 0 0 0 0 0 0 0
Port P60 qIn output mode Port P61 Write ******** Port latch Port P62 Read ******** Port latch qIn input mode Port P63 Write ******** Port latch Port P64 Read ******** Value of pin Port P65 Nothing is arranged for these bits. When these bits are read out, the contents are undefined.
!! !!
Fig. 2.1.3 Structure of port P6
Port P9
b7 b6 b5 b4 b3 b2 b1 b0 Port P9 (P9: address 1216)
b
Name
Functions
qIn output mode Write ******** Port latch Read ******** Port latch qIn input mode Write ******** Port latch Read ******** Value of pin
At reset R W
0
0 Port P90 1 Port P91
0 0 0 0 0 0 0
2 Nothing is arranged for these bits. When these 3 bits are read out, the contents are undefined. 4 5 6 7
! ! ! ! ! !
! ! ! ! ! !
Fig. 2.1.4 Structure of port P9
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APPLICATION
2.1 I/O port Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (i = 0, 2, 4, 5, 7, 8) (PiD: addresses 0116, 0516, 0916, 0B16, 0F16, 1116)
b
Name
Functions
0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode (Note)
At reset R W
0 0 0 0 0 0 0 0
0 Port Pi direction register 1 2 3 4 5 6 7
Note: Bit 7 of the port P4 direction register (address 0916) does not have direction register function because P47 is input port. When writing to bit 7 of the port P4 direction register, write "0" to the bit.
Fig. 2.1.5 Structure of port Pi (i = 0, 2, 4, 5, 7, 8) direction register
Port P6 direction register
b7 b6 b5 b4 b3 b2 b1 b0 Port P6 direction register (P6D: address 0D16)
b
Name
Functions
At reset R W
0 0 0 0 0 0 0 0
0 Port P6 direction register 1 2 3 4 5 6 7
0 : Port P60 input mode 1 : Port P60 output mode 0 : Port P61 input mode 1 : Port P61 output mode 0 : Port P62 input mode 1 : Port P62 output mode 0 : Port P63 input mode 1 : Port P63 output mode 0 : Port P64 input mode 1 : Port P64 output mode 0 : Port P65 input mode 1 : Port P65 output mode Nothing is arranged for these bits. When these bits are read out, the contents are undefined.
!! !!
Fig. 2.1.6 Structure of port P6 direction register
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APPLICATION
2.1 I/O port
Port P9 direction register
b7 b6 b5 b4 b3 b2 b1 b0 Port P9 direction register (P9D: address 1316)
b
Name
Functions
At reset R W
0 0 0 0 0 0 0 0
0 : Port P90 input mode 1 : Port P90 output mode 0 : Port P91 input mode 1 : Port P91 output mode 2 Nothing is arranged for these bits. When these 3 bits are read out, the contents are undefined. 4 5 6 7
0 Port P9 direction register 1
! ! ! ! ! !
! ! ! ! ! !
Fig. 2.1.7 Structure of port P9 direction register
Pull-up control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Pull-up control register 1 (PULL1: address 0EF016)
b
0 1 2 3 4 5 6 7
Name
Ports P50, P51 pullup control Ports P52, P53 pullup control Ports P54, P55 pullup control Ports P56, P57 pullup control
Functions
At reset R W
0 0 0 0 0 0 0 0
0: No pull-up 1: Pull-up 0: No pull-up 1: Pull-up 0: No pull-up 1: Pull-up 0: No pull-up 1: Pull-up 0: No pull-up Port P61 pull-up 1: Pull-up control Ports P62, P63 pull- 0: No pull-up 1: Pull-up up control Ports P64, P65 pull- 0: No pull-up up control 1: Pull-up Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are "0".
Note: The pin set to output port is cut off from pull-up control.
Fig. 2.1.8 Structure of pull-up control register 1
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APPLICATION
2.1 I/O port
Pull-up control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Pull-up control register 2 (PULL2: address 0EF116)
b
Name
Functions
At reset R W
0 0 0 0 0 0 0 0
0 Ports P70, P71 pullup control 1 Ports P72, P73 pullup control 2 Ports P74, P75 pullup control 3 Ports P76, P77 pullup control 4 Ports P84, P85 pullup control 5 Ports P86, P87 pullup control 6 Ports P90, P91 pullup control
0: No pull-up 1: Pull-up 0: No pull-up 1: Pull-up 0: No pull-up 1: Pull-up 0: No pull-up 1: Pull-up 0: No pull-up 1: Pull-up 0: No pull-up 1: Pull-up 0: No pull-up 1: Pull-up Nothing is arranged for this bit. This is a write 7 disabled bit. When this bit is read out, the contents are "0".
Note: The pin set to output port is cut off from pull-up control.
Fig. 2.1.9 Structure of pull-up control register 2 2.1.3 Terminate unused pins Table 2.1.1 Termination of unused pins Pins Termination P1, P3 Open at "H" output state. P5, P61-P65, P7, * Set to the input mode and connect each to VCC or VSS through a resistor of 1 k to P84-P87, P9 10 k. * Set to the * Set to the 10 k. * Set to the P0, P2, P80-P83 * Set to the 10 k. * Set to the P40-P46, P60 P47 VREF XOUT AVSS, VEE output mode and open at "L" or "H" output state. input mode and connect each to VCC or VSS through a resistor of 1 k to output mode and open at "L" output state. input mode and connect each to VCC or VSS through a resistor of 1 k to output mode and open at "H" output state.
Disable INT2 interrupt and connect to VCC or VSS through a resistor of 1 K to 10 k. Open Open (only when using external clock) Connect to VSS (GND).
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2.1 I/O port
2.1.4 Notes on use (1) Notes in standby state In standby stateV1 for low-power dissipation, do not make input levels of an input port and an I/O port "undefined", especially for I/O ports of the P-channel open-drain and the N-channel open-drain. Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a resistor. When determining a resistance value, note the following points: * External circuit * Variation of output levels during the ordinary operation When using built-in pull-up resistor, note on varied current values: * When setting as an input port : Fix its input level * When setting as an output port : Prevent current from flowing out to external q Reason Even when setting as an output port with its direction register, in the following state : * P-channel......when the content of the port latch is "0" * N-channel......when the content of the port latch is "1" the transistor becomes the OFF state, which causes the ports to be the high-impedance state. Note that the level becomes "undefined" depending on external circuits. Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of a input port and an I/O port are "undefined". This may cause power source current. V1 standby state: stop mode by executing STP instruction wait mode by executing WIT instruction (2) N-channel open-drain port P40-P42, P45, P46, P60 of N-channel open-drain output ports have the built-in hysteresis circuit for input. In standby state for low-power dissipation, do not make these pins floating state. q Reason When power sources for pull-up of these pins are cut off in standby state, these ports become floating. Accordingly, a current may flow from Vcc to Vss through the built-in hysteresis circuit.
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APPLICATION
2.1 I/O port
(3) Modifying port latch of I/O port with bit managing instruction When the port latch of an I/O port is modified with the bit managing instruction V2, the value of the unspecified bit may be changed. q Reason The bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an I/O port, the following is executed to all bits of the port latch. *As for bit which is set for input port: The pin state is read in the CPU, and is written to this bit after bit managing. *As for bit which is set for output port: The bit value is read in the CPU, and is written to this bit after bit managing. Note the following: *Even when a port which is set as an output port is changed for an input port, its port latch holds the output data. *As for a bit of which is set for an input port, its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its port latch contents. V2 Bit managing instructions: SEB and CLB instructions (4) Pull-up control When each port which has built-in pull-up resistor (P5, P61-P65, P7, P84-P87, P9) is set to output port, pull-up control of corresponding port become invalid. (Pull-up cannot be set.) q Reason Pull-up control is valid only when each direction register is set to the input mode.
2.1.5 Termination of unused pins (1) Terminate unused pins Output ports : Open Input ports : Connect each pin to VCC or VSS through each resistor of 1 k to 10 k. As for pins whose potential affects to operation modes such as pin INT or others, select the VCC pin or the VSS pin according to their operation mode. I/O ports : * Set the I/O ports for the input mode and connect them to VCC or VSS through each resistor of 1 k to 10 k. Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the I/O ports for the output mode and open them at "L" or "H". * When opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. Thus, the potential at these pins is undefined and the power source current may increase in the input mode. With regard to an effects on the system, thoroughly perform system evaluation on the user side. * Since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program.
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2.1 I/O port
(2) Termination remarks Input ports and I/O ports : Do not open in the input mode. q Reason * The power source current may increase depending on the first-stage circuit. * An effect due to noise may be easily produced as compared with proper termination and shown on the above. I/O ports : When setting for the input mode, do not connect to VCC or VSS directly. q Reason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between a port and VCC (or VSS). I/O ports : When setting for the input mode, do not connect multiple ports in a lump to VCC or VSS through a resistor. q Reason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between ports. * At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less) from microcomputer pins.
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APPLICATION
2.2 Timer
2.2 Timer
This paragraph explains the registers setting method and the notes relevant to the timers. 2.2.1 Memory map
002016 002116 002216 002316 002416 002516 002716 002816 002916 002A16 002C16 002D16 002E16 002F16
Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer 4 (T4) Timer 5 (T5) Timer 6 (T6) Timer 6 PWM register (T6PWM) Timer 12 mode register (T12M) Timer 34 mode register (T34M) Timer 56 mode register (T56M) Timer X (low-order) (TXL) Timer X (high-order) (TXH) Timer X mode register 1 (TXM1) Timer X mode register 2 (TXM2)
003C16 003D16 003E16 003F16
Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2)
Fig. 2.2.1 Memory map of registers relevant to timers
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APPLICATION
2.2 Timer
2.2.2 Relevant registers (1) 8-bit timer
Timer i
b7 b6 b5 b4 b3 b2 b1 b0 Timer i (i = 1, 3, 4, 5, 6) (Ti: addresses 2016, 2216, 2316, 2416, 2516)
b
Functions
At reset R W
1 1 1 1 1 1 1 1
0 * Set timer i count value. 1 * The value set in this register is written to both 2 the timer i and the timer i latch at one time. 3 * When the timer i is read out, the count value 4 of the timer i is read out. 5 6 7
Fig. 2.2.2 Structure of Timer i (i=1, 3, 4, 5, 6)
Timer 2
b7 b6 b5 b4 b3 b2 b1 b0 Timer 2 (T2: address 2116)
b
Functions
At reset R W
1 0 0 0 0 0 0 0
0 * Set timer 2 count value. 1 * The value set in this register is written to both 2 the timer 2 and the timer 2 latch at one time. 3 * When the timer 2 is read out, the count value 4 of the timer 2 is read out. 5 6 7
Fig. 2.2.3 Structure of Timer 2
Timer 6 PWM register
b7 b6 b5 b4 b3 b2 b1 b0 Timer 6 PWM register (T6PWM: address 2716)
b
0 1 2 3 4 5 6 7
Functions
* In timer 6 PWM1 mode "L" level width of PWM rectangular waveform is set. * Duty of PWM rectangular waveform: n/(n + m) Period: (n + m) x ts n = timer 6 set value m = timer 6 PWM register set value ts = timer 6 count source period At n = 0, all PWM output "L". At m = 0, all PWM output "H". (However, n = 0 has priority.) * Selection of timer 6 PWM1 mode Set "1" to the timer 6 operation mode selection bit.
At reset R W
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Fig. 2.2.4 Structure of Timer 6 PWM register
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APPLICATION
2.2 Timer
Timer 12 mode register
b7 b6 b5 b4 b3 b2 b1 b0 Timer 12 mode register (T12M: address 2816)
b
0 1 2 3
Name
Timer 1 count stop bit Timer 2 count stop bit Timer 1 count source selection bits
Functions
0: Count operation 1: Count stop 0: Count operation 1: Count stop
b3 b2
At reset R W
0 0 0
0 0: f(XIN)/8 or f(XCIN)/16 0 1: f(XCIN) 1 0: f(XIN)/16 or f(XCIN)/32 1 1: f(XIN)/64 or f(XCIN)/128
4 Timer 2 count source selection bits 5
b5 b4
0 0: Timer 1 underflow 0 1: f(XCIN) 1 0: External count input CNTR0 1 1: Not available 0: I/O port 6 Timer 1 output selection bit (P45) 1: Timer 1 output 7 Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are "0".
0 0 0 0
Fig. 2.2.5 Structure of Timer 12 mode register
Timer 34 mode register
b7 b6 b5 b4 b3 b2 b1 b0 Timer 34 mode register (T34M: address 2916)
b
Name
Functions
0: Count operation 1: Count stop 0: Count operation 1: Count stop
b3 b2
At reset R W
0 0 0
0 Timer 3 count stop bit 1 Timer 4 count stop bit Timer 3 count 2 source selection 3 bits 4 Timer 4 count source selection bits 5
0 0: f(XIN)/8 or f(XCIN)/16 0 1: Timer 2 underflow 1 0: f(XIN)/16 or f(XCIN)/32 1 1: f(XIN)/64 or f(XCIN)/128
b5 b4
0 0: f(XIN)/8 or f(XCIN)/16 0 1: Timer 3 underflow 1 0: External count input CNTR1 (Note) 1 1: Not available 0: I/O port 6 Timer 3 output selection bit (P46) 1: Timer 3 output 7 Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are "0".
0 0 0 0
Note: In the mask option type P, CNTR1 function cannot be used.
Fig. 2.2.6 Structure of Timer 34 mode register
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2.2 Timer
Timer 56 mode register
b7 b6 b5 b4 b3 b2 b1 b0 Timer 56 mode register (T56M: address 2A16)
b
Name
Functions
0: Count operation 1: Count stop 0: Count operation 1: Count stop 0: f(XIN)/8 or f(XCIN)/16 1: Timer 4 underflow 0: Timer mode 1: PWM mode
b5 b4
At reset R W
0 0 0 0 0 0 0
0 Timer 5 count stop bit 1 Timer 6 count stop bit 2 Timer 5 count source selection bit 3 Timer 6 operation mode selection bit 4 Timer 6 count source selection 5 bits
6 Timer 6 (PWM) output selection bit (P44) 7 Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are "0".
0 0: f(XIN)/8 or f(XCIN)/16 0 1: Timer 5 underflow 1 0: Timer 4 underflow 1 1: Not available 0: I/O port 1: Timer 6 output
0
Fig. 2.2.7 Structure of Timer 56 mode register (2) 16-bit timer
Timer X (low-order, high-order)
b7 b6 b5 b4 b3 b2 b1 b0 Timer X (low-order, high-order) (TXL, TXH: addresses 2C16, 2D16)
b
Functions
At reset R W
1 1 1 1 1 1 1 1
0 * Set timer X count value. 1 * When the timer X write control bit of the timer X mode register 1 is "0", the value is written to 2 timer X and the latch at one time. 3 When the timer X write control bit of the timer X mode register 1 is "1", the value is written 4 only to the latch. 5 * The timer X count value is read out by reading 6 this register. 7
Notes 1: When reading and writing, perform them to both the highorder and low-order bytes. 2: Read both registers in order of TXH and TXL following. 3: Write both registers in order of TXL and TXH following. 4: Do not read both registers during a write, and do not write to both registers during a read.
Fig. 2.2.8 Structure of Timer X (low-order, high-order)
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APPLICATION
2.2 Timer
Timer X mode register 1
b7 b6 b5 b4 b3 b2 b1 b0 Timer X mode register 1 (TXM1: address 2E16)
b
Name
Functions
0 : Write value in latch and counter 1 : Write value in latch only
At reset R W
0
0 Timer X write control bit
b2 b1 1 Timer X count 0 0: f(XIN)/2 or f(XCIN)/4 source selection bits 0 1: f(XIN)/8 or f(XCIN)/16 1 0: f(XIN)/64 or f(XCIN)/128 2 1 1: Not available 3 Nothing is arranged for this bit. This is write disabled bit. When this bit is read out, the contents are "0".
0 0 0
4 Timer X operating mode bits 5
b5 b4
0
0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode
0
6 CNTR2 active edge 0 : *Count at rising edge in event counter mode switch bit *Start from "H" output in pulse output mode *Measure "H" pulse width in pulse width measurement mode 1 : *Count at falling edge in event counter mode *Start from "L" output in pulse output mode *Measure "L" pulse width in pulse width measurement mode 7 Timer X stop control bit 0 : Count operating 1 : Count stop
0
0
Fig. 2.2.9 Structure of Timer X mode register 1
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2.2 Timer
Timer X mode register 2
b7 b6 b5 b4 b3 b2 b1 b0 Timer X mode register 2 (TXM2: address 2F16)
b
Name
bit (P85)
Functions
0: Real time port function is invalid 1: Real time port function is valid 0: Real time port function is invalid 1: Real time port function is valid 0: "L" output 1: "H" output 0: "L" output 1: "H" output
At reset R W
0
0 Real time port control
1 Real time port control
bit (P86)
0 0 0 0 0 0 0 0
2 P85 data for real time
port
3 P86 data for real time
port
4 Nothing is arranged for these bits. These are 5 write disabled bits. When these bits are read 6 out, the contents are "0". 7
Fig. 2.2.10 Structure of Timer X mode register 2
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APPLICATION
2.2 Timer
(3) 8-bit timer, 16-bit timer
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1 : address 3C16)
b
Name
Functions
0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued
At reset R W
0 V
0 INT0 interrupt request bit 1 INT1 interrupt request bit
0
V
2 INT2 interrupt 0 : No interrupt request request bit issued Remote controller 1 : Interrupt request issued /counter overflow interrupt request bit 3 Serial I/O1 interrupt 0 : No interrupt request issued request bit Serial I/O automatic 1 : Interrupt request issued transfer interrupt request bit 4 Timer X interrupt request bit 5 Timer 1 interrupt request bit 6 Timer 2 interrupt request bit 7 Timer 3 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued
0
V
0
V
0
V
0
V
0
V
0
V
V: "0" can be set by software, but "1" cannot be set.
Fig. 2.2.11 Structure of Interrupt request register 1
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2.2 Timer
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 2 (IREQ2 : address 3D16)
b
Name
Functions
At reset R W
0 0 0 0 0 V V V V V
0 Timer 4 interrupt 0 : No interrupt request issued request bit (Note) 1 : Interrupt request issued 1 Timer 5 interrupt 0 : No interrupt request issued request bit 1 : Interrupt request issued 0 : No interrupt request issued 2 Timer 6 interrupt 1 : Interrupt request issued request bit 3 Serial I/O2 receive 0 : No interrupt request issued interrupt request bit 1 : Interrupt request issued 0 : No interrupt request issued 4 INT3/Serial I/O2 1 : Interrupt request issued transmit interrupt request bit (Note) 0 : No interrupt request issued 5 INT4 interrupt 1 : Interrupt request issued request bit A-D converter interrupt request bit 0 : No interrupt request issued 6 FLD blanking interrupt request bit 1 : Interrupt request issued FLD digit interrupt request bit 7 Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are "0".
0
V
0
V
0
V: "0" can be set by software, but "1" cannot be set. Note: In the mask option type P, if timer 4 interrupt whose count source is CNTR1 input and INT3 interrupt are selected, these bits do not become "1".
Fig. 2.2.12 Structure of Interrupt request register 2
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APPLICATION
2.2 Timer
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1 : address 3E16)
b
Name
Functions
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
At reset R W
0 0 0
0 INT0 interrupt enable bit 1 INT1 interrupt enable bit 2 INT2 interrupt enable bit Remote controller /counter overflow interrupt enable bit 3 Serial I/O1 interrupt enable bit Serial I/O automatic transfer interrupt enable bit Timer X interrupt 4 enable bit 5 Timer 1 interrupt enable bit 6 Timer 2 interrupt enable bit 7 Timer 3 interrupt enable bit
0 : Interrupt disabled 1 : Interrupt enabled
0
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
0 0 0 0
Fig. 2.2.13 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2 (ICON2 : address 3F16)
b
Name
Functions
At reset R W
0 0 Timer 4 interrupt 0 : interrupt disabled enable bit (Note) 1 : Interrupt enabled 0 1 Timer 5 interrupt 0 : interrupt disabled enable bit 1 : Interrupt enabled 0 2 Timer 6 interrupt 0 : interrupt disabled enable bit 1 : Interrupt enabled 0 3 Serial I/O2 receive 0 : interrupt disabled interrupt enable bit 1 : Interrupt enabled 0 0 : interrupt disabled 4 INT3/Serial I/O2 1 : Interrupt enabled transmit interrupt enable bit (Note) 0 5 INT4 interrupt 0 : interrupt disabled 1 : Interrupt enabled enable bit A-D converter interrupt enable bit 0 6 FLD blanking 0 : interrupt disabled interrupt enable bit 1 : Interrupt enabled FLD digit interrupt enable bit 7 Fix "0" to this bit. 0 Note: In the mask option type P, timer 4 interrupt whose count source is CNTR1 input and INT3 interrupt are not available.
Fig. 2.2.14 Structure of Interrupt control register 2 2-18
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APPLICATION
2.2 Timer
2.2.3 Timer application examples (1) Basic functions and uses [Function 1] Control of event interval (Timer 1 to Timer 6, Timer X: timer mode) When a certain time, by setting a count value to each timer, has passed, the timer interrupt request occurs. |
